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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-06-12 16:21:47 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-06-12 16:21:47 +0000 |
| commit | a7f3bbcfab9d54387517c2a52e56bfefee092901 (patch) | |
| tree | 18c3cd95448ba54673aa1e588e8eb50ab3cbc705 /src/arch/sparc/isa/formats/mem | |
| parent | 1493ceda8fe242776423e30f83db0774f6558ad4 (diff) | |
| download | gem5-a7f3bbcfab9d54387517c2a52e56bfefee092901.tar.xz | |
Make microOp vs microop and macroOp vs macroop capitilization consistent.
src/arch/x86/isa/macroop.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code.
src/arch/x86/isa/microops/base.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation.
--HG--
extra : convert_revision : 6f4bacfa334c42732c845f9a7f211cbefc73f96f
Diffstat (limited to 'src/arch/sparc/isa/formats/mem')
| -rw-r--r-- | src/arch/sparc/isa/formats/mem/blockmem.isa | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index e19016bd0..caf5bb8ce 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -248,14 +248,14 @@ def template BlockMemConstructor {{ : %(base_class)s("%(mnemonic)s", machInst) { %(constructor)s; - microOps[0] = new %(class_name)s_0(machInst); - microOps[1] = new %(class_name)s_1(machInst); - microOps[2] = new %(class_name)s_2(machInst); - microOps[3] = new %(class_name)s_3(machInst); - microOps[4] = new %(class_name)s_4(machInst); - microOps[5] = new %(class_name)s_5(machInst); - microOps[6] = new %(class_name)s_6(machInst); - microOps[7] = new %(class_name)s_7(machInst); + microops[0] = new %(class_name)s_0(machInst); + microops[1] = new %(class_name)s_1(machInst); + microops[2] = new %(class_name)s_2(machInst); + microops[3] = new %(class_name)s_3(machInst); + microops[4] = new %(class_name)s_4(machInst); + microops[5] = new %(class_name)s_5(machInst); + microops[6] = new %(class_name)s_6(machInst); + microops[7] = new %(class_name)s_7(machInst); } }}; @@ -289,9 +289,9 @@ let {{ for microPc in range(8): flag_code = '' if (microPc == 7): - flag_code = "flags[IsLastMicroOp] = true;" + flag_code = "flags[IsLastMicroop] = true;" elif (microPc == 0): - flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;" + flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroop] = true;" else: flag_code = "flags[IsDelayedCommit] = true;" pcedCode = matcher.sub("Frd_%d" % microPc, code) |