Merge zizzer:/bk/newmem

into  zower.eecs.umich.edu:/eecshome/m5/newmem

src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/system.cc:
    Hand Merge

--HG--
extra : convert_revision : d5e0c97caebb616493e2f642e915969d7028109c

4 files changed, 13 insertions, 7 deletions

diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa
index 56e933763..e8762a205 100644
--- a/src/arch/sparc/isa/formats/basic.isa
+++ b/src/arch/sparc/isa/formats/basic.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright (c) 2006-2007 The Regents of The University of Michigan
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -38,6 +38,7 @@ def template BasicExecPanic {{
         Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
         {
             panic("Execute method called when it shouldn't!");
+            M5_DUMMY_RETURN
         }
 }};
 
@@ -71,6 +72,7 @@ def template BasicExecute {{
         {
             Fault fault = NoFault;
 
+            %(fp_enable_check)s;
             %(op_decl)s;
             %(op_rd)s;
             %(code)s;
diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa
index 363aca1a1..f877b8790 100644
--- a/src/arch/sparc/isa/formats/integerop.isa
+++ b/src/arch/sparc/isa/formats/integerop.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright (c) 2006-2007 The Regents of The University of Michigan
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -154,7 +154,7 @@ output decoder {{
         bool IntOp::printPseudoOps(std::ostream &os, Addr pc,
                 const SymbolTable *symbab) const
         {
-            if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
+            if(!std::strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
             {
                 printMnemonic(os, "mov");
                 printSrcReg(os, 1);
@@ -168,7 +168,7 @@ output decoder {{
         bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
                 const SymbolTable *symbab) const
         {
-            if(!strcmp(mnemonic, "or"))
+            if(!std::strcmp(mnemonic, "or"))
             {
                 if(_numSrcRegs > 0 && _srcRegIdx[0] == 0)
                 {
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
index 352e963b3..9795d2342 100644
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -476,7 +476,6 @@ let {{
             faultCode = ''
         return (header_output, decoder_output, exec_output, decode_block)
 
-
     def doTwinLoadFormat(code, faultCode, name, Name, asi, opt_flags):
         addrCalcReg = 'EA = Rs1 + Rs2 + offset;'
         addrCalcImm = 'EA = Rs1 + imm + offset;'
@@ -492,10 +491,11 @@ let {{
             pcedCode = ''
             if (microPc == 1):
                 flag_code = "flags[IsLastMicroOp] = true;"
-                pcedCode = matcher.sub("RdHigh", code)
+                pcedCode = "RdLow = uReg0;\n"
+                pcedCode += matcher.sub("RdHigh", code)
             else:
                 flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;"
-                pcedCode = matcher.sub("RdLow", code)
+                pcedCode = matcher.sub("uReg0", code)
             iop = InstObjParams(name, Name, 'TwinMem',
                     {"code": pcedCode, "ea_code": addrCalcReg,
                     "fault_check": faultCode, "micro_pc": microPc,
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 5bb4e1fe6..dbaabdca4 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -141,6 +141,7 @@ def template LoadExecute {{
         {
             Fault fault = NoFault;
             Addr EA;
+            %(fp_enable_check)s;
             %(op_decl)s;
             %(op_rd)s;
             %(ea_code)s;
@@ -170,6 +171,7 @@ def template LoadInitiateAcc {{
         {
             Fault fault = NoFault;
             Addr EA;
+            %(fp_enable_check)s;
             %(op_decl)s;
             %(op_rd)s;
             %(ea_code)s;
@@ -210,6 +212,7 @@ def template StoreExecute {{
             //It should be optomized out in all the others
             bool storeCond = true;
             Addr EA;
+            %(fp_enable_check)s;
             %(op_decl)s;
             %(op_rd)s;
             %(ea_code)s;
@@ -241,6 +244,7 @@ def template StoreInitiateAcc {{
             Fault fault = NoFault;
             bool storeCond = true;
             Addr EA;
+            %(fp_enable_check)s;
             %(op_decl)s;
             %(op_rd)s;
             %(ea_code)s;