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authorGabe Black <gblack@eecs.umich.edu>2007-01-22 22:31:48 -0800
committerGabe Black <gblack@eecs.umich.edu>2007-01-22 22:31:48 -0800
commit1352e55ceb2d78a9a36451636b672cd6daf8550e (patch)
treed7c797f46cd00cc76628a4a65329f2f2dd966cbe /src/arch/sparc/isa/formats
parent45c3f1747c78aff3495edfe2cbe35fbb7a67f2a4 (diff)
parent60eaa03d72a13863596e64343d7407af1cab51c5 (diff)
downloadgem5-1352e55ceb2d78a9a36451636b672cd6daf8550e.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmemo3 src/sim/byteswap.hh: Hand Merge --HG-- extra : convert_revision : 640d33ad0c416934e8a5107768e7f1dce6709ca8
Diffstat (limited to 'src/arch/sparc/isa/formats')
-rw-r--r--src/arch/sparc/isa/formats/mem/blockmem.isa4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
index 62ac4b43a..352e963b3 100644
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -451,6 +451,8 @@ let {{
flag_code = ''
if (microPc == 7):
flag_code = "flags[IsLastMicroOp] = true;"
+ elif (microPc == 0):
+ flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;"
else:
flag_code = "flags[IsDelayedCommit] = true;"
pcedCode = matcher.sub("Frd_%d" % microPc, code)
@@ -492,7 +494,7 @@ let {{
flag_code = "flags[IsLastMicroOp] = true;"
pcedCode = matcher.sub("RdHigh", code)
else:
- flag_code = "flags[IsDelayedCommit] = true;"
+ flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;"
pcedCode = matcher.sub("RdLow", code)
iop = InstObjParams(name, Name, 'TwinMem',
{"code": pcedCode, "ea_code": addrCalcReg,