SPARC: Clean up some historical style issues.

12 files changed, 184 insertions, 211 deletions

diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa
index cad759b3e..bef8af2cd 100644
--- a/src/arch/sparc/isa/formats/basic.isa
+++ b/src/arch/sparc/isa/formats/basic.isa
@@ -35,7 +35,8 @@ def template BasicExecDeclare {{
 
 // Definitions of execute methods that panic.
 def template BasicExecPanic {{
-        Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
+        Fault
+        execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
         {
             panic("Execute method called when it shouldn't!");
             M5_DUMMY_RETURN
@@ -91,7 +92,8 @@ def template BasicConstructorWithMnemonic {{
 
 // Basic instruction class execute method template.
 def template BasicExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+        Fault
+        %(class_name)s::execute(%(CPU_exec_context)s *xc,
                 Trace::InstRecord *traceData) const
         {
             Fault fault = NoFault;
@@ -101,8 +103,7 @@ def template BasicExecute {{
             %(op_rd)s;
             %(code)s;
 
-            if(fault == NoFault)
-            {
+            if (fault == NoFault) {
                 %(op_wb)s;
             }
             return fault;
diff --git a/src/arch/sparc/isa/formats/branch.isa b/src/arch/sparc/isa/formats/branch.isa
index e62e0035a..b7d0dde72 100644
--- a/src/arch/sparc/isa/formats/branch.isa
+++ b/src/arch/sparc/isa/formats/branch.isa
@@ -127,28 +127,29 @@ output decoder {{
 
         template class BranchNBits<30>;
 
-        std::string Branch::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
+        std::string
+        Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         {
             std::stringstream response;
 
             printMnemonic(response, mnemonic);
             printRegArray(response, _srcRegIdx, _numSrcRegs);
-            if(_numDestRegs && _numSrcRegs)
+            if (_numDestRegs && _numSrcRegs)
                     response << ", ";
             printDestReg(response, 0);
 
             return response.str();
         }
 
-        std::string BranchImm13::generateDisassembly(Addr pc,
+        std::string
+        BranchImm13::generateDisassembly(Addr pc,
                 const SymbolTable *symtab) const
         {
             std::stringstream response;
 
             printMnemonic(response, mnemonic);
             printRegArray(response, _srcRegIdx, _numSrcRegs);
-            if(_numSrcRegs > 0)
+            if (_numSrcRegs > 0)
                 response << ", ";
             ccprintf(response, "0x%x", imm);
             if (_numDestRegs > 0)
@@ -158,7 +159,8 @@ output decoder {{
             return response.str();
         }
 
-        std::string BranchDisp::generateDisassembly(Addr pc,
+        std::string
+        BranchDisp::generateDisassembly(Addr pc,
                 const SymbolTable *symtab) const
         {
             std::stringstream response;
@@ -170,10 +172,10 @@ output decoder {{
             printMnemonic(response, mnemonic);
             ccprintf(response, "0x%x", target);
 
-            if(symtab && symtab->findNearestSymbol(target, symbol, symbolAddr))
-            {
+            if (symtab &&
+                    symtab->findNearestSymbol(target, symbol, symbolAddr)) {
                 ccprintf(response, " <%s", symbol);
-                if(symbolAddr != target)
+                if (symbolAddr != target)
                     ccprintf(response, "+%d>", target - symbolAddr);
                 else
                     ccprintf(response, ">");
@@ -187,7 +189,7 @@ def template JumpExecute {{
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                 Trace::InstRecord *traceData) const
         {
-            //Attempt to execute the instruction
+            // Attempt to execute the instruction
             Fault fault = NoFault;
 
             %(op_decl)s;
@@ -196,9 +198,8 @@ def template JumpExecute {{
             PCS = PCS;
             %(code)s;
 
-            if(fault == NoFault)
-            {
-                //Write the resulting state to the execution context
+            if (fault == NoFault) {
+                // Write the resulting state to the execution context
                 %(op_wb)s;
             }
 
@@ -207,10 +208,11 @@ def template JumpExecute {{
 }};
 
 def template BranchExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+        Fault
+        %(class_name)s::execute(%(CPU_exec_context)s *xc,
                 Trace::InstRecord *traceData) const
         {
-            //Attempt to execute the instruction
+            // Attempt to execute the instruction
             Fault fault = NoFault;
 
             %(op_decl)s;
@@ -222,9 +224,8 @@ def template BranchExecute {{
                 %(fail)s;
             }
 
-            if(fault == NoFault)
-            {
-                //Write the resulting state to the execution context
+            if (fault == NoFault) {
+                // Write the resulting state to the execution context
                 %(op_wb)s;
             }
 
diff --git a/src/arch/sparc/isa/formats/formats.isa b/src/arch/sparc/isa/formats/formats.isa
index 8125e6349..f19e16547 100644
--- a/src/arch/sparc/isa/formats/formats.isa
+++ b/src/arch/sparc/isa/formats/formats.isa
@@ -26,34 +26,34 @@
 //
 // Authors: Gabe Black
 
-//Include the basic format
-//Templates from this format are used later
+// Include the basic format
+// Templates from this format are used later
 ##include "basic.isa"
 
-//Include base classes for microcoding instructions
+// Include base classes for microcoding instructions
 ##include "micro.isa"
 
-//Include the noop format
+// Include the noop format
 ##include "nop.isa"
 
-//Include the integerOp and integerOpCc format
+// Include the integerOp and integerOpCc format
 ##include "integerop.isa"
 
-//Include the memory formats
+// Include the memory formats
 ##include "mem/mem.isa"
 
-//Include the trap format
+// Include the trap format
 ##include "trap.isa"
 
-//Include the unimplemented format
+// Include the unimplemented format
 ##include "unimp.isa"
 
-//Include the "unknown" format
+// Include the "unknown" format
 ##include "unknown.isa"
 
-//Include the priveleged mode format
+// Include the priveleged mode format
 ##include "priv.isa"
 
-//Include the branch format
+// Include the branch format
 ##include "branch.isa"
 
diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa
index 55af7e5b3..e9536f495 100644
--- a/src/arch/sparc/isa/formats/integerop.isa
+++ b/src/arch/sparc/isa/formats/integerop.isa
@@ -142,7 +142,7 @@ output header {{
 
 def template SetHiDecode {{
     {
-        if(RD == 0 && IMM22 == 0)
+        if (RD == 0 && IMM22 == 0)
             return (SparcStaticInst *)(new Nop("nop", machInst, No_OpClass));
         else
             return (SparcStaticInst *)(new %(class_name)s(machInst));
@@ -151,11 +151,11 @@ def template SetHiDecode {{
 
 output decoder {{
 
-        bool IntOp::printPseudoOps(std::ostream &os, Addr pc,
+        bool
+        IntOp::printPseudoOps(std::ostream &os, Addr pc,
                 const SymbolTable *symbab) const
         {
-            if(!std::strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
-            {
+            if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) {
                 printMnemonic(os, "mov");
                 printSrcReg(os, 1);
                 ccprintf(os, ", ");
@@ -165,25 +165,21 @@ output decoder {{
             return false;
         }
 
-        bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
+        bool
+        IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
                 const SymbolTable *symbab) const
         {
-            if(!std::strcmp(mnemonic, "or"))
-            {
-                if(_numSrcRegs > 0 && _srcRegIdx[0] == 0)
-                {
-                    if(imm == 0)
+            if (!std::strcmp(mnemonic, "or")) {
+                if (_numSrcRegs > 0 && _srcRegIdx[0] == 0) {
+                    if (imm == 0) {
                         printMnemonic(os, "clr");
-                    else
-                    {
+                    } else {
                         printMnemonic(os, "mov");
                         ccprintf(os, " 0x%x, ", imm);
                     }
                     printDestReg(os, 0);
                     return true;
-                }
-                else if(imm == 0)
-                {
+                } else if (imm == 0) {
                     printMnemonic(os, "mov");
                     printSrcReg(os, 0);
                     ccprintf(os, ", ");
@@ -194,41 +190,42 @@ output decoder {{
             return false;
         }
 
-        std::string IntOp::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
+        std::string
+        IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         {
             std::stringstream response;
 
-            if(printPseudoOps(response, pc, symtab))
+            if (printPseudoOps(response, pc, symtab))
                 return response.str();
             printMnemonic(response, mnemonic);
             printRegArray(response, _srcRegIdx, _numSrcRegs);
-            if(_numDestRegs && _numSrcRegs)
+            if (_numDestRegs && _numSrcRegs)
                 response << ", ";
             printDestReg(response, 0);
             return response.str();
         }
 
-        std::string IntOpImm::generateDisassembly(Addr pc,
+        std::string
+        IntOpImm::generateDisassembly(Addr pc,
                 const SymbolTable *symtab) const
         {
             std::stringstream response;
 
-            if(printPseudoOps(response, pc, symtab))
+            if (printPseudoOps(response, pc, symtab))
                 return response.str();
             printMnemonic(response, mnemonic);
             printRegArray(response, _srcRegIdx, _numSrcRegs);
-            if(_numSrcRegs > 0)
+            if (_numSrcRegs > 0)
                 response << ", ";
             ccprintf(response, "0x%x", imm);
-            if(_numDestRegs > 0)
+            if (_numDestRegs > 0)
                 response << ", ";
             printDestReg(response, 0);
             return response.str();
         }
 
-        std::string SetHi::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
+        std::string
+        SetHi::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         {
             std::stringstream response;
 
@@ -249,9 +246,8 @@ def template IntOpExecute {{
             %(op_rd)s;
             %(code)s;
 
-            //Write the resulting state to the execution context
-            if(fault == NoFault)
-            {
+            // Write the resulting state to the execution context
+            if (fault == NoFault) {
                 %(cc_code)s;
                 %(op_wb)s;
             }
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
index 020dc326f..c397d2675 100644
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -100,8 +100,7 @@ output decoder {{
             bool save = flags[IsStore];
 
             printMnemonic(response, mnemonic);
-            if(save)
-            {
+            if (save) {
                 printReg(response, _srcRegIdx[0]);
                 ccprintf(response, ", ");
             }
@@ -110,8 +109,7 @@ output decoder {{
             ccprintf(response, " + ");
             printReg(response, _srcRegIdx[!save ? 1 : 2]);
             ccprintf(response, " ]");
-            if(load)
-            {
+            if (load) {
                 ccprintf(response, ", ");
                 printReg(response, _destRegIdx[0]);
             }
@@ -127,19 +125,17 @@ output decoder {{
             bool save = flags[IsStore];
 
             printMnemonic(response, mnemonic);
-            if(save)
-            {
+            if (save) {
                 printReg(response, _srcRegIdx[1]);
                 ccprintf(response, ", ");
             }
             ccprintf(response, "[ ");
             printReg(response, _srcRegIdx[0]);
-            if(imm >= 0)
+            if (imm >= 0)
                 ccprintf(response, " + 0x%x ]", imm);
             else
                 ccprintf(response, " + -0x%x ]", -imm);
-            if(load)
-            {
+            if (load) {
                 ccprintf(response, ", ");
                 printReg(response, _destRegIdx[0]);
             }
@@ -156,14 +152,14 @@ def template BlockMemDeclare {{
         class %(class_name)s : public %(base_class)s
         {
           public:
-            //Constructor
+            // Constructor
             %(class_name)s(ExtMachInst machInst);
 
           protected:
             class %(class_name)s_0 : public %(base_class)sMicro
             {
               public:
-                //Constructor
+                // Constructor
                 %(class_name)s_0(ExtMachInst machInst);
                 %(BasicExecDeclare)s
                 %(InitiateAccDeclare)s
@@ -173,7 +169,7 @@ def template BlockMemDeclare {{
             class %(class_name)s_1 : public %(base_class)sMicro
             {
               public:
-                //Constructor
+                // Constructor
                 %(class_name)s_1(ExtMachInst machInst);
                 %(BasicExecDeclare)s
                 %(InitiateAccDeclare)s
@@ -183,7 +179,7 @@ def template BlockMemDeclare {{
             class %(class_name)s_2 : public %(base_class)sMicro
             {
               public:
-                //Constructor
+                // Constructor
                 %(class_name)s_2(ExtMachInst machInst);
                 %(BasicExecDeclare)s
                 %(InitiateAccDeclare)s
@@ -193,7 +189,7 @@ def template BlockMemDeclare {{
             class %(class_name)s_3 : public %(base_class)sMicro
             {
               public:
-                //Constructor
+                // Constructor
                 %(class_name)s_3(ExtMachInst machInst);
                 %(BasicExecDeclare)s
                 %(InitiateAccDeclare)s
@@ -203,7 +199,7 @@ def template BlockMemDeclare {{
             class %(class_name)s_4 : public %(base_class)sMicro
             {
               public:
-                //Constructor
+                // Constructor
                 %(class_name)s_4(ExtMachInst machInst);
                 %(BasicExecDeclare)s
                 %(InitiateAccDeclare)s
@@ -213,7 +209,7 @@ def template BlockMemDeclare {{
             class %(class_name)s_5 : public %(base_class)sMicro
             {
               public:
-                //Constructor
+                // Constructor
                 %(class_name)s_5(ExtMachInst machInst);
                 %(BasicExecDeclare)s
                 %(InitiateAccDeclare)s
@@ -223,7 +219,7 @@ def template BlockMemDeclare {{
             class %(class_name)s_6 : public %(base_class)sMicro
             {
               public:
-                //Constructor
+                // Constructor
                 %(class_name)s_6(ExtMachInst machInst);
                 %(BasicExecDeclare)s
                 %(InitiateAccDeclare)s
@@ -233,7 +229,7 @@ def template BlockMemDeclare {{
             class %(class_name)s_7 : public %(base_class)sMicro
             {
               public:
-                //Constructor
+                // Constructor
                 %(class_name)s_7(ExtMachInst machInst);
                 %(BasicExecDeclare)s
                 %(InitiateAccDeclare)s
diff --git a/src/arch/sparc/isa/formats/mem/mem.isa b/src/arch/sparc/isa/formats/mem/mem.isa
index db45e226d..17d6c5c5e 100644
--- a/src/arch/sparc/isa/formats/mem/mem.isa
+++ b/src/arch/sparc/isa/formats/mem/mem.isa
@@ -32,14 +32,14 @@
 // Mem formats
 //
 
-//Include mem utility templates and functions
+// Include mem utility templates and functions
 ##include "util.isa"
 
-//Include the basic memory format
+// Include the basic memory format
 ##include "basicmem.isa"
 
-//Include the block memory format
+// Include the block memory format
 ##include "blockmem.isa"
 
-//Include the load/store and cas memory format
+// Include the load/store and cas memory format
 ##include "swap.isa"
diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa
index 046f89822..1ab82da59 100644
--- a/src/arch/sparc/isa/formats/mem/swap.isa
+++ b/src/arch/sparc/isa/formats/mem/swap.isa
@@ -27,14 +27,14 @@
 // Authors: Gabe Black
 //          Ali Saidi
 
-//This template provides the execute functions for a swap
+// This template provides the execute functions for a swap
 def template SwapExecute {{
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                 Trace::InstRecord *traceData) const
         {
             Fault fault = NoFault;
-            //This is to support the conditional store in cas instructions.
-            //It should be optomized out in all the others
+            // This is to support the conditional store in cas instructions.
+            // It should be optomized out in all the others
             bool storeCond = true;
             Addr EA;
             %(fp_enable_check)s;
@@ -45,25 +45,21 @@ def template SwapExecute {{
             %(ea_code)s;
             DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
             %(fault_check)s;
-            if(fault == NoFault)
-            {
+            if (fault == NoFault) {
                 %(code)s;
             }
-            if(storeCond && fault == NoFault)
-            {
+            if (storeCond && fault == NoFault) {
                 %(EA_trunc)s
                 fault = xc->write((uint%(mem_acc_size)s_t)Mem,
                         EA, %(asi_val)s, &mem_data);
             }
-            if(fault == NoFault)
-            {
-                    //Handle the swapping
-                    %(postacc_code)s;
+            if (fault == NoFault) {
+                // Handle the swapping
+                %(postacc_code)s;
             }
-            if(fault == NoFault)
-            {
-                    //Write the resulting state to the execution context
-                    %(op_wb)s;
+            if (fault == NoFault) {
+                // Write the resulting state to the execution context
+                %(op_wb)s;
             }
 
             return fault;
@@ -86,12 +82,10 @@ def template SwapInitiateAcc {{
             DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
             %(fault_check)s;
 
-            if(fault == NoFault)
-            {
+            if (fault == NoFault) {
                 %(code)s;
             }
-            if(fault == NoFault)
-            {
+            if (fault == NoFault) {
                 %(EA_trunc)s
                 fault = xc->write((uint%(mem_acc_size)s_t)Mem,
                         EA, %(asi_val)s, &mem_data);
@@ -111,15 +105,13 @@ def template SwapCompleteAcc {{
 
             uint64_t mem_data = pkt->get<uint%(mem_acc_size)s_t>();
 
-            if(fault == NoFault)
-            {
-                    //Handle the swapping
-                    %(postacc_code)s;
+            if (fault == NoFault) {
+                // Handle the swapping
+                %(postacc_code)s;
             }
-            if(fault == NoFault)
-            {
-                    //Write the resulting state to the execution context
-                    %(op_wb)s;
+            if (fault == NoFault) {
+                // Write the resulting state to the execution context
+                %(op_wb)s;
             }
 
             return fault;
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 667b9a23a..ca673566b 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -79,21 +79,18 @@ output decoder {{
             bool store = flags[IsStore];
 
             printMnemonic(response, mnemonic);
-            if(store)
-            {
+            if (store) {
                 printReg(response, _srcRegIdx[0]);
                 ccprintf(response, ", ");
             }
             ccprintf(response, "[");
-            if(_srcRegIdx[!store ? 0 : 1] != 0)
-            {
+            if (_srcRegIdx[!store ? 0 : 1] != 0) {
                 printSrcReg(response, !store ? 0 : 1);
                 ccprintf(response, " + ");
             }
             printSrcReg(response, !store ? 1 : 2);
             ccprintf(response, "]");
-            if(load)
-            {
+            if (load) {
                 ccprintf(response, ", ");
                 printReg(response, _destRegIdx[0]);
             }
@@ -109,23 +106,20 @@ output decoder {{
             bool save = flags[IsStore];
 
             printMnemonic(response, mnemonic);
-            if(save)
-            {
+            if (save) {
                 printReg(response, _srcRegIdx[0]);
                 ccprintf(response, ", ");
             }
             ccprintf(response, "[");
-            if(_srcRegIdx[!save ? 0 : 1] != 0)
-            {
+            if (_srcRegIdx[!save ? 0 : 1] != 0) {
                 printReg(response, _srcRegIdx[!save ? 0 : 1]);
                 ccprintf(response, " + ");
             }
-            if(imm >= 0)
+            if (imm >= 0)
                 ccprintf(response, "0x%x]", imm);
             else
                 ccprintf(response, "-0x%x]", -imm);
-            if(load)
-            {
+            if (load) {
                 ccprintf(response, ", ");
                 printReg(response, _destRegIdx[0]);
             }
@@ -134,7 +128,7 @@ output decoder {{
         }
 }};
 
-//This template provides the execute functions for a load
+// This template provides the execute functions for a load
 def template LoadExecute {{
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                 Trace::InstRecord *traceData) const
@@ -147,19 +141,16 @@ def template LoadExecute {{
             %(ea_code)s;
             DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
             %(fault_check)s;
-            if(fault == NoFault)
-            {
+            if (fault == NoFault) {
                 %(EA_trunc)s
                 fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s);
             }
-            if(fault == NoFault)
-            {
+            if (fault == NoFault) {
                 %(code)s;
             }
-            if(fault == NoFault)
-            {
-                    //Write the resulting state to the execution context
-                    %(op_wb)s;
+            if (fault == NoFault) {
+                // Write the resulting state to the execution context
+                %(op_wb)s;
             }
 
             return fault;
@@ -178,8 +169,7 @@ def template LoadInitiateAcc {{
             %(ea_code)s;
             DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
             %(fault_check)s;
-            if(fault == NoFault)
-            {
+            if (fault == NoFault) {
                 %(EA_trunc)s
                 fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s);
             }
@@ -196,22 +186,21 @@ def template LoadCompleteAcc {{
             %(op_rd)s;
             Mem = pkt->get<typeof(Mem)>();
             %(code)s;
-            if(fault == NoFault)
-            {
+            if (fault == NoFault) {
                 %(op_wb)s;
             }
             return fault;
         }
 }};
 
-//This template provides the execute functions for a store
+// This template provides the execute functions for a store
 def template StoreExecute {{
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                 Trace::InstRecord *traceData) const
         {
             Fault fault = NoFault;
-            //This is to support the conditional store in cas instructions.
-            //It should be optomized out in all the others
+            // This is to support the conditional store in cas instructions.
+            // It should be optomized out in all the others
             bool storeCond = true;
             Addr EA;
             %(fp_enable_check)s;
@@ -220,20 +209,17 @@ def template StoreExecute {{
             %(ea_code)s;
             DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
             %(fault_check)s;
-            if(fault == NoFault)
-            {
+            if (fault == NoFault) {
                 %(code)s;
             }
-            if(storeCond && fault == NoFault)
-            {
+            if (storeCond && fault == NoFault) {
                 %(EA_trunc)s
                 fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
                         EA, %(asi_val)s, 0);
             }
-            if(fault == NoFault)
-            {
-                    //Write the resulting state to the execution context
-                    %(op_wb)s;
+            if (fault == NoFault) {
+                // Write the resulting state to the execution context
+                %(op_wb)s;
             }
 
             return fault;
@@ -254,12 +240,10 @@ def template StoreInitiateAcc {{
             %(ea_code)s;
             DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
             %(fault_check)s;
-            if(fault == NoFault)
-            {
+            if (fault == NoFault) {
                 %(code)s;
             }
-            if(storeCond && fault == NoFault)
-            {
+            if (storeCond && fault == NoFault) {
                 %(EA_trunc)s
                 fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
                         EA, %(asi_val)s, 0);
@@ -276,17 +260,17 @@ def template StoreCompleteAcc {{
         }
 }};
 
-//This delcares the initiateAcc function in memory operations
+// This delcares the initiateAcc function in memory operations
 def template InitiateAccDeclare {{
     Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
 }};
 
-//This declares the completeAcc function in memory operations
+// This declares the completeAcc function in memory operations
 def template CompleteAccDeclare {{
     Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
 }};
 
-//Here are some code snippets which check for various fault conditions
+// Here are some code snippets which check for various fault conditions
 let {{
     LoadFuncs = [LoadExecute, LoadInitiateAcc, LoadCompleteAcc]
     StoreFuncs = [StoreExecute, StoreInitiateAcc, StoreCompleteAcc]
@@ -294,15 +278,15 @@ let {{
     # The LSB can be zero, since it's really the MSB in doubles and quads
     # and we're dealing with doubles
     BlockAlignmentFaultCheck = '''
-        if(RD & 0xe)
+        if (RD & 0xe)
             fault = new IllegalInstruction;
-        else if(EA & 0x3f)
+        else if (EA & 0x3f)
             fault = new MemAddressNotAligned;
     '''
     TwinAlignmentFaultCheck = '''
-        if(RD & 0x1)
+        if (RD & 0x1)
             fault = new IllegalInstruction;
-        else if(EA & 0xf)
+        else if (EA & 0xf)
             fault = new MemAddressNotAligned;
     '''
     # XXX Need to take care of pstate.hpriv as well. The lower ASIs
@@ -310,10 +294,10 @@ let {{
     # those that are only available in hpriv
     AlternateASIPrivFaultCheck = '''
         if ((!bits(Pstate,2,2) && !bits(Hpstate,2,2) &&
-             !AsiIsUnPriv((ASI)EXT_ASI)) ||
-            (!bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI)))
+             !asiIsUnPriv((ASI)EXT_ASI)) ||
+            (!bits(Hpstate,2,2) && asiIsHPriv((ASI)EXT_ASI)))
             fault = new PrivilegedAction;
-        else if (AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
+        else if (asiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
             fault = new PrivilegedAction;
     '''
 
@@ -324,18 +308,18 @@ let {{
     '''
 }};
 
-//A simple function to generate the name of the macro op of a certain
-//instruction at a certain micropc
+// A simple function to generate the name of the macro op of a certain
+// instruction at a certain micropc
 let {{
     def makeMicroName(name, microPc):
             return name + "::" + name + "_" + str(microPc)
 }};
 
-//This function properly generates the execute functions for one of the
-//templates above. This is needed because in one case, ea computation,
-//fault checks and the actual code all occur in the same function,
-//and in the other they're distributed across two. Also note that for
-//execute functions, the name of the base class doesn't matter.
+// This function properly generates the execute functions for one of the
+// templates above. This is needed because in one case, ea computation,
+// fault checks and the actual code all occur in the same function,
+// and in the other they're distributed across two. Also note that for
+// execute functions, the name of the base class doesn't matter.
 let {{
     def doSplitExecute(execute, name, Name, asi, opt_flags, microParam):
         microParam["asi_val"] = asi;
diff --git a/src/arch/sparc/isa/formats/micro.isa b/src/arch/sparc/isa/formats/micro.isa
index b5a53a68b..2138ba6f5 100644
--- a/src/arch/sparc/isa/formats/micro.isa
+++ b/src/arch/sparc/isa/formats/micro.isa
@@ -26,9 +26,10 @@
 //
 // Authors: Gabe Black
 
-//This delcares the initiateAcc function in memory operations
+// This delcares the initiateAcc function in memory operations
 def template MacroInitiateAcc {{
-    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const
+    Fault
+    initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const
     {
         panic("Tried to execute a macroop directly!\n");
         return NoFault;
@@ -36,17 +37,18 @@ def template MacroInitiateAcc {{
 }};
 
 def template MacroCompleteAcc {{
-    Fault completeAcc(PacketPtr, %(CPU_exec_context)s *,
-            Trace::InstRecord *) const
+    Fault
+    completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const
     {
         panic("Tried to execute a macroop directly!\n");
         return NoFault;
     }
 }};
 
-//This template provides the execute functions for a store
+// This template provides the execute functions for a store
 def template MacroExecute {{
-    Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
+    Fault
+    execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
     {
         panic("Tried to execute a macroop directly!\n");
         return NoFault;
@@ -60,7 +62,7 @@ output header {{
           protected:
             const uint32_t numMicroops;
 
-            //Constructor.
+            // Constructor.
             SparcMacroInst(const char *mnem, ExtMachInst _machInst,
                     OpClass __opClass, uint32_t _numMicroops)
                         : SparcStaticInst(mnem, _machInst, __opClass),
@@ -96,7 +98,7 @@ output header {{
         class SparcMicroInst : public SparcStaticInst
         {
           protected:
-            //Constructor.
+            // Constructor.
             SparcMicroInst(const char *mnem,
                     ExtMachInst _machInst, OpClass __opClass)
                         : SparcStaticInst(mnem, _machInst, __opClass)
@@ -117,7 +119,7 @@ output header {{
         class SparcDelayedMicroInst : public SparcMicroInst
         {
           protected:
-            //Constructor.
+            // Constructor.
             SparcDelayedMicroInst(const char *mnem,
                     ExtMachInst _machInst, OpClass __opClass)
                         : SparcMicroInst(mnem, _machInst, __opClass)
@@ -129,7 +131,8 @@ output header {{
 
 output decoder {{
 
-        std::string SparcMacroInst::generateDisassembly(Addr pc,
+        std::string
+        SparcMacroInst::generateDisassembly(Addr pc,
                 const SymbolTable *symtab) const
         {
             std::stringstream response;
diff --git a/src/arch/sparc/isa/formats/nop.isa b/src/arch/sparc/isa/formats/nop.isa
index 63c541288..a1c650369 100644
--- a/src/arch/sparc/isa/formats/nop.isa
+++ b/src/arch/sparc/isa/formats/nop.isa
@@ -82,7 +82,7 @@ def template NopExecute {{
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                 Trace::InstRecord *traceData) const
         {
-            //Nothing to see here, move along
+            // Nothing to see here, move along
             return NoFault;
         }
 }};
diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa
index 795a22958..56f1cdbd9 100644
--- a/src/arch/sparc/isa/formats/priv.isa
+++ b/src/arch/sparc/isa/formats/priv.isa
@@ -50,12 +50,12 @@ output header {{
                     const SymbolTable *symtab) const;
         };
 
-        //This class is for instructions that explicitly read control
-        //registers. It provides a special generateDisassembly function.
+        // This class is for instructions that explicitly read control
+        // registers. It provides a special generateDisassembly function.
         class RdPriv : public Priv
         {
           protected:
-            //Constructor
+            // Constructor
             RdPriv(const char *mnem, ExtMachInst _machInst,
                     OpClass __opClass, char const * _regName) :
                 Priv(mnem, _machInst, __opClass), regName(_regName)
@@ -68,12 +68,12 @@ output header {{
             char const * regName;
         };
 
-        //This class is for instructions that explicitly write control
-        //registers. It provides a special generateDisassembly function.
+        // This class is for instructions that explicitly write control
+        // registers. It provides a special generateDisassembly function.
         class WrPriv : public Priv
         {
           protected:
-            //Constructor
+            // Constructor
             WrPriv(const char *mnem, ExtMachInst _machInst,
                     OpClass __opClass, char const * _regName) :
                 Priv(mnem, _machInst, __opClass), regName(_regName)
@@ -102,12 +102,12 @@ output header {{
             int32_t imm;
         };
 
-        //This class is for instructions that explicitly write control
-        //registers. It provides a special generateDisassembly function.
+        // This class is for instructions that explicitly write control
+        // registers. It provides a special generateDisassembly function.
         class WrPrivImm : public PrivImm
         {
           protected:
-            //Constructor
+            // Constructor
             WrPrivImm(const char *mnem, ExtMachInst _machInst,
                     OpClass __opClass, char const * _regName) :
                 PrivImm(mnem, _machInst, __opClass), regName(_regName)
@@ -122,8 +122,8 @@ output header {{
 }};
 
 output decoder {{
-        std::string Priv::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
+        std::string
+        Priv::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         {
             std::stringstream response;
 
@@ -132,8 +132,8 @@ output decoder {{
             return response.str();
         }
 
-        std::string RdPriv::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
+        std::string
+        RdPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         {
             std::stringstream response;
 
@@ -145,18 +145,17 @@ output decoder {{
             return response.str();
         }
 
-        std::string WrPriv::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
+        std::string
+        WrPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         {
             std::stringstream response;
 
             printMnemonic(response, mnemonic);
 
             ccprintf(response, " ");
-            //If the first reg is %g0, don't print it.
-            //This improves readability
-            if(_srcRegIdx[0] != 0)
-            {
+            // If the first reg is %g0, don't print it.
+            // This improves readability
+            if (_srcRegIdx[0] != 0) {
                 printSrcReg(response, 0);
                 ccprintf(response, ", ");
             }
@@ -174,10 +173,9 @@ output decoder {{
             printMnemonic(response, mnemonic);
 
             ccprintf(response, " ");
-            //If the first reg is %g0, don't print it.
-            //This improves readability
-            if(_srcRegIdx[0] != 0)
-            {
+            // If the first reg is %g0, don't print it.
+            // This improves readability
+            if (_srcRegIdx[0] != 0) {
                 printSrcReg(response, 0);
                 ccprintf(response, ", ");
             }
@@ -203,11 +201,11 @@ def template PrivExecute {{
         %(op_decl)s;
         %(op_rd)s;
 
-        //If the processor isn't in privileged mode, fault out right away
-        if(%(check)s)
+        // If the processor isn't in privileged mode, fault out right away
+        if (%(check)s)
             return new PrivilegedAction;
 
-        if(%(tlCheck)s)
+        if (%(tlCheck)s)
             return new IllegalInstruction;
 
         Fault fault = NoFault;
diff --git a/src/arch/sparc/isa/formats/trap.isa b/src/arch/sparc/isa/formats/trap.isa
index 66eff35d4..018379f57 100644
--- a/src/arch/sparc/isa/formats/trap.isa
+++ b/src/arch/sparc/isa/formats/trap.isa
@@ -55,8 +55,8 @@ output header {{
 }};
 
 output decoder {{
-        std::string Trap::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
+        std::string
+        Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         {
             std::stringstream response;
 
@@ -71,7 +71,8 @@ output decoder {{
 }};
 
 def template TrapExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+        Fault
+        %(class_name)s::execute(%(CPU_exec_context)s *xc,
                 Trace::InstRecord *traceData) const
         {
             Fault fault = NoFault;
@@ -83,7 +84,8 @@ def template TrapExecute {{
 }};
 
 def template FpUnimplExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+        Fault
+        %(class_name)s::execute(%(CPU_exec_context)s *xc,
                 Trace::InstRecord *traceData) const
         {
             Fault fault = NoFault;
@@ -113,8 +115,8 @@ output header {{
             {
             }
 
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const
+            std::string
+            generateDisassembly(Addr pc,  const SymbolTable *symtab) const
             {
                 return mnemonic;
             }