Style: Replace some tabs with spaces.

1 files changed, 93 insertions, 93 deletions

diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index dfc71f419..047451ae7 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -72,71 +72,71 @@ def operands {{
     # For clarity, descriptions that depend on unsigned behavior should
     # explicitly specify '.uq'.
 
-    'Rd': 		('IntReg', 'udw', 'RD', 'IsInteger', 1),
+    'Rd':               ('IntReg', 'udw', 'RD', 'IsInteger', 1),
     # The Rd from the previous window
-    'Rd_prev':		('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2),
+    'Rd_prev':          ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2),
     # The Rd from the next window
-    'Rd_next':		('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3),
+    'Rd_next':          ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3),
     # For microcoded twin load instructions, RdTwin appears in the "code"
     # for the instruction is replaced by RdLow or RdHigh by the format
     # before it's processed by the iop.
     # The low (even) register of a two register pair
-    'RdLow': 		('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4),
+    'RdLow':            ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4),
     # The high (odd) register of a two register pair
-    'RdHigh':		('IntReg', 'udw', 'RD | 1', 'IsInteger', 5),
-    'Rs1': 		('IntReg', 'udw', 'RS1', 'IsInteger', 6),
-    'Rs2': 		('IntReg', 'udw', 'RS2', 'IsInteger', 7),
+    'RdHigh':           ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5),
+    'Rs1':              ('IntReg', 'udw', 'RS1', 'IsInteger', 6),
+    'Rs2':              ('IntReg', 'udw', 'RS2', 'IsInteger', 7),
     # A microcode register. Right now, this is the only one.
-    'uReg0':		('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8),
+    'uReg0':            ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8),
     # Because double and quad precision register numbers are decoded
     # differently, they get different operands. The single precision versions
     # have an s post pended to their name.
-    'Frds':		('FloatReg', 'sf', 'RD', 'IsFloating', 10),
-    #'Frd':		('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
-    'Frd_low':		('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
-    'Frd_high':		('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
+    'Frds':             ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
+    #'Frd':             ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
+    'Frd_low':          ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
+    'Frd_high':         ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
     # Each Frd_N refers to the Nth double precision register from Frd.
     # Note that this adds twice N to the register number.
-    #'Frd_0':		('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
-    'Frd_0_low':	('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
-    'Frd_0_high':	('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
-    #'Frd_1':		('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
-    'Frd_1_low':	('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10),
-    'Frd_1_high':	('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10),
-    #'Frd_2':		('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
-    'Frd_2_low':	('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10),
-    'Frd_2_high':	('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10),
-    #'Frd_3':		('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
-    'Frd_3_low':	('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10),
-    'Frd_3_high':	('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10),
-    #'Frd_4':		('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
-    'Frd_4_low':	('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10),
-    'Frd_4_high':	('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10),
-    #'Frd_5':		('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
-    'Frd_5_low':	('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10),
-    'Frd_5_high':	('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10),
-    #'Frd_6':		('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
-    'Frd_6_low':	('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10),
-    'Frd_6_high':	('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10),
-    #'Frd_7':		('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
-    'Frd_7_low':	('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10),
-    'Frd_7_high':	('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10),
-    'Frs1s':		('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
-    #'Frs1':		('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
-    'Frs1_low':		('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11),
-    'Frs1_high':	('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11),
-    'Frs2s':		('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
-    #'Frs2':		('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
-    'Frs2_low':		('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12),
-    'Frs2_high':	('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12),
+    #'Frd_0':           ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
+    'Frd_0_low':        ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
+    'Frd_0_high':       ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
+    #'Frd_1':           ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
+    'Frd_1_low':        ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10),
+    'Frd_1_high':       ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10),
+    #'Frd_2':           ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
+    'Frd_2_low':        ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10),
+    'Frd_2_high':       ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10),
+    #'Frd_3':           ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
+    'Frd_3_low':        ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10),
+    'Frd_3_high':       ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10),
+    #'Frd_4':           ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
+    'Frd_4_low':        ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10),
+    'Frd_4_high':       ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10),
+    #'Frd_5':           ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
+    'Frd_5_low':        ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10),
+    'Frd_5_high':       ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10),
+    #'Frd_6':           ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
+    'Frd_6_low':        ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10),
+    'Frd_6_high':       ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10),
+    #'Frd_7':           ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
+    'Frd_7_low':        ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10),
+    'Frd_7_high':       ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10),
+    'Frs1s':            ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
+    #'Frs1':            ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
+    'Frs1_low':         ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11),
+    'Frs1_high':        ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11),
+    'Frs2s':            ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
+    #'Frs2':            ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
+    'Frs2_low':         ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12),
+    'Frs2_high':        ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12),
     'PC':               ('PCState', 'udw', 'pc', (None, None, 'IsControl'), 30),
     'NPC':              ('PCState', 'udw', 'npc', (None, None, 'IsControl'), 30),
     'NNPC':             ('PCState', 'udw', 'nnpc', (None, None, 'IsControl'), 30),
     # Registers which are used explicitly in instructions
-    'R0':  		('IntReg', 'udw', '0', None, 6),
-    'R1':  		('IntReg', 'udw', '1', None, 7),
-    'R15': 		('IntReg', 'udw', '15', 'IsInteger', 8),
-    'R16': 		('IntReg', 'udw', '16', None, 9),
+    'R0':               ('IntReg', 'udw', '0', None, 6),
+    'R1':               ('IntReg', 'udw', '1', None, 7),
+    'R15':              ('IntReg', 'udw', '15', 'IsInteger', 8),
+    'R16':              ('IntReg', 'udw', '16', None, 9),
     'O0':               ('IntReg', 'udw', '8', 'IsInteger', 10),
     'O1':               ('IntReg', 'udw', '9', 'IsInteger', 11),
     'O2':               ('IntReg', 'udw', '10', 'IsInteger', 12),
@@ -145,55 +145,55 @@ def operands {{
     'O5':               ('IntReg', 'udw', '13', 'IsInteger', 15),
 
     # Control registers
-#   'Y':		('ControlReg', 'udw', 'MISCREG_Y', None, 40),
-#   'Ccr':		('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
-    'Y':		('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40),
-    'Ccr':		('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41),
-    'Asi':		('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
-    'Fprs':		('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
-    'Pcr':		('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
-    'Pic':		('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
-#   'Gsr':		('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46),
-    'Gsr':		('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46),
-    'Softint':		('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
-    'SoftintSet':	('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
-    'SoftintClr':	('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),
-    'TickCmpr':		('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),
-    'Stick':		('ControlReg', 'udw', 'MISCREG_STICK', None, 51),
-    'StickCmpr':	('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),
+#   'Y':                ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
+#   'Ccr':              ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
+    'Y':                ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40),
+    'Ccr':              ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41),
+    'Asi':              ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
+    'Fprs':             ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
+    'Pcr':              ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
+    'Pic':              ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
+#   'Gsr':              ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46),
+    'Gsr':              ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46),
+    'Softint':          ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
+    'SoftintSet':       ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
+    'SoftintClr':       ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),
+    'TickCmpr':         ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),
+    'Stick':            ('ControlReg', 'udw', 'MISCREG_STICK', None, 51),
+    'StickCmpr':        ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),
 
-    'Tpc':		('ControlReg', 'udw', 'MISCREG_TPC', None, 53),
-    'Tnpc':		('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
-    'Tstate':		('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
-    'Tt':		('ControlReg', 'udw', 'MISCREG_TT', None, 56),
-    'Tick':		('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
-    'Tba':		('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
-    'Pstate':		('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
-    'Tl':		('ControlReg', 'udw', 'MISCREG_TL', None, 60),
-    'Pil':		('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
-    'Cwp':		('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62),
-#   'Cansave':		('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
-#   'Canrestore':	('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
-#   'Cleanwin':		('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
-#   'Otherwin':		('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
-#   'Wstate':		('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
-    'Cansave':		('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63),
-    'Canrestore':	('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64),
-    'Cleanwin':		('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65),
-    'Otherwin':		('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66),
-    'Wstate':		('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67),
+    'Tpc':              ('ControlReg', 'udw', 'MISCREG_TPC', None, 53),
+    'Tnpc':             ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
+    'Tstate':           ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
+    'Tt':               ('ControlReg', 'udw', 'MISCREG_TT', None, 56),
+    'Tick':             ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
+    'Tba':              ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
+    'Pstate':           ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
+    'Tl':               ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
+    'Pil':              ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
+    'Cwp':              ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62),
+#   'Cansave':          ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
+#   'Canrestore':       ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
+#   'Cleanwin':         ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
+#   'Otherwin':         ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
+#   'Wstate':           ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
+    'Cansave':          ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63),
+    'Canrestore':       ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64),
+    'Cleanwin':         ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65),
+    'Otherwin':         ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66),
+    'Wstate':           ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67),
     'Gl':               ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
 
-    'Hpstate':		('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
-    'Htstate':		('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
-    'Hintp':		('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
-    'Htba':		('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
-    'HstickCmpr':	('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
-    'Hver':		('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
-    'StrandStsReg':	('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),
+    'Hpstate':          ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
+    'Htstate':          ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
+    'Hintp':            ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
+    'Htba':             ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
+    'HstickCmpr':       ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
+    'Hver':             ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
+    'StrandStsReg':     ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),
 
-    'Fsr':		('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
+    'Fsr':              ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
     # Mem gets a large number so it's always last
-    'Mem': 		('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
+    'Mem':              ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
 
 }};