summaryrefslogtreecommitdiff
path: root/src/arch/sparc/isa/operands.isa
diff options
context:
space:
mode:
authorKevin Lim <ktlim@umich.edu>2006-11-10 15:35:06 -0500
committerKevin Lim <ktlim@umich.edu>2006-11-10 15:35:06 -0500
commite89eaf8b801b39713b28f2df7e89ea8a518974ec (patch)
tree15102b11266b888577742c5e814bd66d1fc510bb /src/arch/sparc/isa/operands.isa
parentb5e68fb54677f601bb00c23af52db8fd6571301f (diff)
parent6d54a77518664bc9064211fcf85958b7e2caa9cc (diff)
downloadgem5-e89eaf8b801b39713b28f2df7e89ea8a518974ec.tar.xz
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem --HG-- extra : convert_revision : 35e2ff6ce62281299ad98dca64ba04a3a8a6757c
Diffstat (limited to 'src/arch/sparc/isa/operands.isa')
-rw-r--r--src/arch/sparc/isa/operands.isa1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index caee20b0c..2d200f568 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -123,6 +123,7 @@ def operands {{
'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
+ 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80),
# Mem gets a large number so it's always last