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authorAli Saidi <saidi@eecs.umich.edu>2007-02-21 21:06:17 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-02-21 21:06:17 -0500
commit7a2ecf9e268bf10fc0a2406f3a928a661e97b5fd (patch)
tree6ed93c5595ee96386bfea26b5ac5b87c46f706fb /src/arch/sparc/isa/operands.isa
parenta329631edbf18d01f5f84b57147bdd69f1e2e6b3 (diff)
downloadgem5-7a2ecf9e268bf10fc0a2406f3a928a661e97b5fd.tar.xz
add pseduo instruction support for sparc
util/m5/Makefile.alpha: Clean up to make it a bit easier to muck with util/m5/Makefile.alpha: Make the makefile more reasonable util/m5/Makefile.alpha: Remove authors from copyright. util/m5/Makefile.alpha: Updated Authors from bk prs info util/m5/Makefile.alpha: bk cp Makefile Makefile.alpha src/arch/sparc/tlb.cc: Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate src/arch/alpha/isa/decoder.isa: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: Rename AlphaPseudo -> PseudoInst since it's all generic src/arch/sparc/isa/bitfields.isa: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/includes.isa: src/arch/sparc/isa/operands.isa: Add support for pseudo instructions in sparc util/m5/Makefile.alpha: util/m5/Makefile.sparc: split off alpha make file and sparc make file for m5 app util/m5/m5.c: ivle and ivlb aren't used anymore util/m5/m5op.h: stdint seems like a more generic better fit here util/m5/m5op_alpha.S: move the op ids into their own header file since we can share them between sparc and alpha --HG-- rename : util/m5/Makefile => util/m5/Makefile.sparc rename : util/m5/m5op.S => util/m5/m5op_alpha.S extra : convert_revision : 490ba2e8b8bc6e28bfc009cedec6b686b28e7834
Diffstat (limited to 'src/arch/sparc/isa/operands.isa')
-rw-r--r--src/arch/sparc/isa/operands.isa6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index f624c3e2b..82e9407de 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -100,6 +100,12 @@ def operands {{
'R1': ('IntReg', 'udw', '1', None, 7),
'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
'R16': ('IntReg', 'udw', '16', None, 9),
+ 'O0': ('IntReg', 'udw', '24', 'IsInteger', 10),
+ 'O1': ('IntReg', 'udw', '25', 'IsInteger', 11),
+ 'O2': ('IntReg', 'udw', '26', 'IsInteger', 12),
+ 'O3': ('IntReg', 'udw', '27', 'IsInteger', 13),
+ 'O4': ('IntReg', 'udw', '28', 'IsInteger', 14),
+ 'O5': ('IntReg', 'udw', '29', 'IsInteger', 15),
# Control registers
# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),