Fixed subtract with carry, and started some work with floating point.

src/arch/sparc/isa/decoder.isa:
    fixed subc, subccc, added decoding for impdep1 to fit with ua2005, and started work on floating point.
src/arch/sparc/isa/operands.isa:
    Added in floating point operands, and changed the numbering of operands.
src/arch/sparc/regfile.hh:
    Fixed some memory errors related to floating point.

--HG--
extra : convert_revision : fa0aef2021a5cf99f175fceeb533fe63eb5f805c

1 files changed, 22 insertions, 22 deletions

diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 9e5c783e8..d250d3672 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -51,12 +51,12 @@ def operands {{
     'RdHigh':		('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
     'Rs1': 		('IntReg', 'udw', 'RS1', 'IsInteger', 4),
     'Rs2': 		('IntReg', 'udw', 'RS2', 'IsInteger', 5),
-    #'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
-    #'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
-    #'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
-    'Mem': 		('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
-    'NPC': 		('NPC', 'udw', None, ( None, None, 'IsControl' ), 4),
-    'NNPC':		('NNPC', 'udw', None, (None, None, 'IsControl' ), 4),
+    'Frd':		('FloatReg', 'df', 'RD', 'IsFloating', 10),
+    'Frs1':		('FloatReg', 'df', 'RS1', 'IsFloating', 11),
+    'Frs2':		('FloatReg', 'df', 'RS2', 'IsFloating', 12),
+    'Mem': 		('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20),
+    'NPC': 		('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
+    'NNPC':		('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
     #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
     #'FPCR':  ('ControlReg', 'uq', 'Fpcr', None, 1),
     'R0':  		('IntReg', 'udw', '0', None, 6),
@@ -65,24 +65,24 @@ def operands {{
     'R16': 		('IntReg', 'udw', '16', None, 9),
 
     # Control registers
-    'Y':		('ControlReg', 'udw', 'MISCREG_Y', None, 12),
-    'Ccr':		('ControlReg', 'udw', 'MISCREG_CCR', None, 17),
-    'Asi':		('ControlReg', 'udw', 'MISCREG_ASI', None, 26),
+    'Y':		('ControlReg', 'udw', 'MISCREG_Y', None, 40),
+    'Ccr':		('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
+    'Asi':		('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
 
-    'Tpc':		('ControlReg', 'udw', 'MISCREG_TPC', None, 28),
-    'Tnpc':		('ControlReg', 'udw', 'MISCREG_TNPC', None, 28),
-    'Tstate':		('ControlReg', 'udw', 'MISCREG_TSTATE', None, 28),
-    'Pstate':		('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
-    'Tl':		('ControlReg', 'udw', 'MISCREG_TL', None, 27),
+    'Tpc':		('ControlReg', 'udw', 'MISCREG_TPC', None, 43),
+    'Tnpc':		('ControlReg', 'udw', 'MISCREG_TNPC', None, 44),
+    'Tstate':		('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45),
+    'Pstate':		('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46),
+    'Tl':		('ControlReg', 'udw', 'MISCREG_TL', None, 47),
 
-    'Cwp':		('ControlReg', 'udw', 'MISCREG_CWP', None, 15),
-    'Cansave':		('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 34),
-    'Canrestore':	('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 35),
-    'Cleanwin':		('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 37),
-    'Otherwin':		('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36),
-    'Wstate':		('ControlReg', 'udw', 'MISCREG_WSTATE', None, 38),
-    'Gl':               ('ControlReg', 'udw', 'MISCREG_GL', None, 12),
+    'Cwp':		('ControlReg', 'udw', 'MISCREG_CWP', None, 48),
+    'Cansave':		('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49),
+    'Canrestore':	('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50),
+    'Cleanwin':		('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51),
+    'Otherwin':		('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52),
+    'Wstate':		('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53),
+    'Gl':               ('ControlReg', 'udw', 'MISCREG_GL', None, 54),
 
-    'Fsr':		('ControlReg', 'udw', 'MISCREG_FSR', None, 47)
+    'Fsr':		('ControlReg', 'udw', 'MISCREG_FSR', None, 55)
 
 }};