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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-10-23 07:55:52 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-10-23 07:55:52 -0400 |
| commit | 20208d00e6566a7946e589184a7ed9dffb54fc74 (patch) | |
| tree | 77764410222fd4f064360a8fa624675121d9f40f /src/arch/sparc/isa/operands.isa | |
| parent | e9908e3c854e534a391448907773ca03c60b13c8 (diff) | |
| download | gem5-20208d00e6566a7946e589184a7ed9dffb54fc74.tar.xz | |
Broke Load/Store instructions into microcode, and partially refactored memory operations in the SPARC ISA description.
--HG--
rename : src/arch/sparc/isa/formats.isa => src/arch/sparc/isa/formats/formats.isa
rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/basicmem.isa
rename : src/arch/sparc/isa/formats/blockmem.isa => src/arch/sparc/isa/formats/mem/blockmem.isa
rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/mem.isa
extra : convert_revision : dbbb00f997a102871b084b209b9fa08c5e1853ee
Diffstat (limited to 'src/arch/sparc/isa/operands.isa')
| -rw-r--r-- | src/arch/sparc/isa/operands.isa | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 40926a5fb..b8b75170b 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -77,7 +77,6 @@ def operands {{ 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12), 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), - 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20), 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), @@ -107,6 +106,8 @@ def operands {{ 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54), 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55), - 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56) + 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56), + # Mem gets a large number so it's always last + 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) }}; |