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authorGabe Black <gblack@eecs.umich.edu>2006-11-10 04:02:39 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-11-10 04:02:39 -0500
commit4aea5deccb948035459583d811837cb6affd1c07 (patch)
treebcbdca54bc15b7d9ac58726282164c9415edac88 /src/arch/sparc/isa/operands.isa
parent232c3f1b270aa04b924442bb6520c65c5a1414e1 (diff)
downloadgem5-4aea5deccb948035459583d811837cb6affd1c07.tar.xz
Fix up instructions to read and write control registers, and got rid of the control register fields which won't work on a big endian host.
--HG-- extra : convert_revision : 1b518873b6e1a073b58cbe27642537d5ae3a604d
Diffstat (limited to 'src/arch/sparc/isa/operands.isa')
-rw-r--r--src/arch/sparc/isa/operands.isa50
1 files changed, 33 insertions, 17 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 80b499b91..caee20b0c 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -80,8 +80,6 @@ def operands {{
'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
- #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
- #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
'R0': ('IntReg', 'udw', '0', None, 6),
'R1': ('IntReg', 'udw', '1', None, 7),
'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
@@ -91,24 +89,42 @@ def operands {{
'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
+ 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
+ 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
+ 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
+ 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 46),
+ 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
+ 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
+ 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),
+ 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),
+ 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51),
+ 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),
- 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 43),
- 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44),
- 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45),
- 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46),
- 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 47),
- 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 48),
+ 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53),
+ 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
+ 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
+ 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56),
+ 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
+ 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
+ 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
+ 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
+ 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
+ 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 62),
+ 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
+ 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
+ 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
+ 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
+ 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
+ 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
- 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 49),
- 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 50),
- 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 51),
- 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 52),
- 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 53),
- 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 54),
- 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 55),
+ 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
+ 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
+ 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
+ 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
+ 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
+ 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
- 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 56),
- 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 57),
+ 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80),
# Mem gets a large number so it's always last
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)