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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-10-29 01:58:37 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-10-29 01:58:37 -0500 |
| commit | 6dddca951151c953fdab6f3e57b9385150d8b90b (patch) | |
| tree | 62b85fcb502db373bafd333e93915a8b562c9c90 /src/arch/sparc/isa/operands.isa | |
| parent | 61c808ae1c79c5674f7c8dc2a7bbb2cddc3d7296 (diff) | |
| download | gem5-6dddca951151c953fdab6f3e57b9385150d8b90b.tar.xz | |
Add an integer microcode register.
--HG--
extra : convert_revision : f23dbfdfe44e8e6cdd6948000669ad4f743b9fb4
Diffstat (limited to 'src/arch/sparc/isa/operands.isa')
| -rw-r--r-- | src/arch/sparc/isa/operands.isa | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index ba2c38e91..80b499b91 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -61,6 +61,7 @@ def operands {{ 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3), 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5), + 'uReg0': ('IntReg', 'udw', 'NumRegularIntRegs+0', 'IsInteger', 6), 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), # Each Frd_N refers to the Nth double precision register from Frd. |