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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-10-12 17:38:06 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-10-12 17:38:06 -0400 |
| commit | 98b00d92fdf89d130630665327143f67ee16d0fe (patch) | |
| tree | 1b9087bd0de013b42fbf57ee3e7e0b977f8a998c /src/arch/sparc/isa/operands.isa | |
| parent | 866dda97782728ee68d7b11e3d2ed4e2d526c901 (diff) | |
| download | gem5-98b00d92fdf89d130630665327143f67ee16d0fe.tar.xz | |
Some support for handling block loads and stores and ASIs properly.
src/arch/sparc/isa/bitfields.isa:
Added a field to retrieve the asi from the ExtMachInst
src/arch/sparc/isa/decoder.isa:
Fixed up how the size of memory operations where handled, and use the new EXT_ASI bit field.
src/arch/sparc/isa/formats.isa:
add includes for the new formats.
src/arch/sparc/isa/formats/basic.isa:
Add a template for BasicDecodeWithMnemonic which is needed by the unimp format.
src/arch/sparc/isa/formats/mem.isa:
Change around the memory format to figure out the memory access width on its own.
src/arch/sparc/isa/operands.isa:
Added support for the operands of block loads/stores which are offset from Frd.
src/arch/sparc/utility.hh:
Encoded the ASI into the ExtMachInst
--HG--
extra : convert_revision : 5c6026a07e3a919e738d27f78beb0faf6b060643
Diffstat (limited to 'src/arch/sparc/isa/operands.isa')
| -rw-r--r-- | src/arch/sparc/isa/operands.isa | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 605816083..b01443d5b 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -52,6 +52,14 @@ def operands {{ 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5), 'Frd': ('FloatReg', 'df', 'RD', 'IsFloating', 10), + 'Frd_0': ('FloatReg', 'df', 'RD', 'IsFloating', 10), + 'Frd_1': ('FloatReg', 'df', 'RD + 1', 'IsFloating', 10), + 'Frd_2': ('FloatReg', 'df', 'RD + 2', 'IsFloating', 10), + 'Frd_3': ('FloatReg', 'df', 'RD + 3', 'IsFloating', 10), + 'Frd_4': ('FloatReg', 'df', 'RD + 4', 'IsFloating', 10), + 'Frd_5': ('FloatReg', 'df', 'RD + 5', 'IsFloating', 10), + 'Frd_6': ('FloatReg', 'df', 'RD + 6', 'IsFloating', 10), + 'Frd_7': ('FloatReg', 'df', 'RD + 7', 'IsFloating', 10), 'Frs1': ('FloatReg', 'df', 'RS1', 'IsFloating', 11), 'Frs2': ('FloatReg', 'df', 'RS2', 'IsFloating', 12), 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20), |