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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-16 12:54:28 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-16 12:54:28 -0500 |
| commit | b9d069167cc4700495a5ccaf938093731208dca8 (patch) | |
| tree | 4c1507c426eb7fff8a37eba8aba11458b80ce092 /src/arch/sparc/isa/operands.isa | |
| parent | fe737603881f620da2c4b14f18158c20487c9960 (diff) | |
| download | gem5-b9d069167cc4700495a5ccaf938093731208dca8.tar.xz | |
Support for twin loads.
src/arch/sparc/isa/decoder.isa:
Changed the names of the twin loads to match the 2005 spec. They still use the old format though.
src/arch/sparc/isa/formats/mem/blockmem.isa:
Added code to generate twin loads
src/arch/sparc/isa/formats/mem/util.isa:
Added an alignment check for twin loads
src/arch/sparc/isa/operands.isa:
Comment explaining twin load operands.
--HG--
extra : convert_revision : ad42821a97dcda17744875b1e5dc00a9642e59b7
Diffstat (limited to 'src/arch/sparc/isa/operands.isa')
| -rw-r--r-- | src/arch/sparc/isa/operands.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 80ed7362c..abb82f88c 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -57,6 +57,9 @@ def operands {{ # For clarity, descriptions that depend on unsigned behavior should # explicitly specify '.uq'. 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), + # For microcoded twin load instructions, RdTwin appears in the "code" + # for the instruction and is replaced by RdLow or RdHigh by the format + # before it's processed by the iop. 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2), 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3), 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), |