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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-17 11:55:24 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-17 11:55:24 -0500 |
| commit | c3ec52346b99d398916765679877686c109e3513 (patch) | |
| tree | 18c5add9cda92e2724a0a9940fd3797795f04916 /src/arch/sparc/isa/operands.isa | |
| parent | c299c2562b68d75eb457c7206d3ec43e4cabcf14 (diff) | |
| parent | 81996f855a2ffb05c70e904040c5da42a0666545 (diff) | |
| download | gem5-c3ec52346b99d398916765679877686c109e3513.tar.xz | |
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/operands.isa:
Hand Merge
--HG--
extra : convert_revision : 4c54544e5c7a61f055ea9b00ccf5f8510df0e6c2
Diffstat (limited to 'src/arch/sparc/isa/operands.isa')
| -rw-r--r-- | src/arch/sparc/isa/operands.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 256f2fa43..2d1c3d3b9 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -62,6 +62,9 @@ def operands {{ 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2), # The Rd from the next window 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3), + # For microcoded twin load instructions, RdTwin appears in the "code" + # for the instruction is replaced by RdLow or RdHigh by the format + # before it's processed by the iop. # The low (even) register of a two register pair 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4), # The high (odd) register of a two register pair |