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authorGabe Black <gblack@eecs.umich.edu>2010-11-11 02:03:58 -0800
committerGabe Black <gblack@eecs.umich.edu>2010-11-11 02:03:58 -0800
commitcdc585e0e8ceb305de83053c488ba041367b7cd6 (patch)
treeea3342231f3fdcbe52e3603294bfc46f072aaef7 /src/arch/sparc/isa/operands.isa
parent0b7967d606cdda184df8df1446852e4aac93331d (diff)
downloadgem5-cdc585e0e8ceb305de83053c488ba041367b7cd6.tar.xz
SPARC: Clean up some historical style issues.
Diffstat (limited to 'src/arch/sparc/isa/operands.isa')
-rw-r--r--src/arch/sparc/isa/operands.isa9
1 files changed, 6 insertions, 3 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 8bf6450be..a72fd12b9 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -48,17 +48,20 @@ output header {{
// A function to "decompress" double and quad floating point
// register numbers stuffed into 5 bit fields. These have their
// MSB put in the LSB position but are otherwise normal.
- static inline unsigned int dfpr(unsigned int regNum)
+ static inline unsigned int
+ dfpr(unsigned int regNum)
{
return (regNum & (~1)) | ((regNum & 1) << 5);
}
- static inline unsigned int dfprl(unsigned int regNum)
+ static inline unsigned int
+ dfprl(unsigned int regNum)
{
return dfpr(regNum) & (~0x1);
}
- static inline unsigned int dfprh(unsigned int regNum)
+ static inline unsigned int
+ dfprh(unsigned int regNum)
{
return dfpr(regNum) | 0x1;
}