diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-23 00:36:42 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-23 00:36:42 -0500 |
| commit | de445b5e9655514d2c58197254c56ce5fd753e81 (patch) | |
| tree | 9f3a17a8c4b50e16e5d66df4a87cffe0d6fa6ddf /src/arch/sparc/isa/operands.isa | |
| parent | 758c78065167ab58d63754827971a149c51282b9 (diff) | |
| download | gem5-de445b5e9655514d2c58197254c56ce5fd753e81.tar.xz | |
Fixes to the isa description.
src/arch/sparc/isa/base.isa:
Fix a constant.
src/arch/sparc/isa/decoder.isa:
Made carry calculation more consistent.
src/arch/sparc/isa/operands.isa:
Use the right constant.
--HG--
extra : convert_revision : 25b3a09ff20d4b8e1a95ee8a983d14ef3cfe73bb
Diffstat (limited to 'src/arch/sparc/isa/operands.isa')
| -rw-r--r-- | src/arch/sparc/isa/operands.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 2d200f568..80ed7362c 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -61,7 +61,7 @@ def operands {{ 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3), 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5), - 'uReg0': ('IntReg', 'udw', 'NumRegularIntRegs+0', 'IsInteger', 6), + 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 6), 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), # Each Frd_N refers to the Nth double precision register from Frd. |