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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-16 12:55:55 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-16 12:55:55 -0500 |
| commit | 91b56d03fc380a044564c5cfc84501f2b2849e5b (patch) | |
| tree | 6b7187dc980e0f3f19c0eb50139b831eeafee824 /src/arch/sparc/isa/operands.isa | |
| parent | 4da37bcd1bc2c42ce5f297a58b4b4bffa4e8cd4f (diff) | |
| parent | c9f18981f9283095548c37aea6e7b2db648b70b0 (diff) | |
| download | gem5-91b56d03fc380a044564c5cfc84501f2b2849e5b.tar.xz | |
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/sparcfs
--HG--
extra : convert_revision : c8718b3df72b8c951c24742e8ce517a93bc23fe9
Diffstat (limited to 'src/arch/sparc/isa/operands.isa')
| -rw-r--r-- | src/arch/sparc/isa/operands.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 80ed7362c..abb82f88c 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -57,6 +57,9 @@ def operands {{ # For clarity, descriptions that depend on unsigned behavior should # explicitly specify '.uq'. 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), + # For microcoded twin load instructions, RdTwin appears in the "code" + # for the instruction and is replaced by RdLow or RdHigh by the format + # before it's processed by the iop. 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2), 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3), 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), |