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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-21 21:06:29 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-21 21:06:29 -0500 |
| commit | f01f8f1be6a536580371428aa3e8e654d97fb868 (patch) | |
| tree | a7d11dc92adeb5c4f01e45452e76430f542c4460 /src/arch/sparc/isa/operands.isa | |
| parent | 06ae2d04455d39acb1db642952e56b6a0359cf22 (diff) | |
| parent | 7a2ecf9e268bf10fc0a2406f3a928a661e97b5fd (diff) | |
| download | gem5-f01f8f1be6a536580371428aa3e8e654d97fb868.tar.xz | |
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : 4105ebbeca59206bece27f229ee810d594fb4310
Diffstat (limited to 'src/arch/sparc/isa/operands.isa')
| -rw-r--r-- | src/arch/sparc/isa/operands.isa | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index f624c3e2b..82e9407de 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -100,6 +100,12 @@ def operands {{ 'R1': ('IntReg', 'udw', '1', None, 7), 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 'R16': ('IntReg', 'udw', '16', None, 9), + 'O0': ('IntReg', 'udw', '24', 'IsInteger', 10), + 'O1': ('IntReg', 'udw', '25', 'IsInteger', 11), + 'O2': ('IntReg', 'udw', '26', 'IsInteger', 12), + 'O3': ('IntReg', 'udw', '27', 'IsInteger', 13), + 'O4': ('IntReg', 'udw', '28', 'IsInteger', 14), + 'O5': ('IntReg', 'udw', '29', 'IsInteger', 15), # Control registers # 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), |