SPARC: Remove parameter that was only ever set to one value.

--HG--
extra : convert_revision : 3c22e576d95bdc7566bbce9b92cf2a6ff153a66f

4 files changed, 52 insertions, 53 deletions

diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index eaeba3e2d..c35b231ff 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1116,76 +1116,75 @@ decode OP default Unknown::unknown()
                                Rd.uw = tmp;
                          }}, MEM_SWAP);
         format LoadAlt {
-            0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
-            0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
-            0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
+            0x10: lduwa({{Rd = Mem.uw;}});
+            0x11: lduba({{Rd = Mem.ub;}});
+            0x12: lduha({{Rd = Mem.uhw;}});
             0x13: decode EXT_ASI {
                 //ASI_LDTD_AIUP
                 0x22: TwinLoad::ldtx_aiup(
                     {{RdLow.udw = (Mem.tudw).a;
-                      RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
+                      RdHigh.udw = (Mem.tudw).b;}});
                 //ASI_LDTD_AIUS
                 0x23: TwinLoad::ldtx_aius(
                     {{RdLow.udw = (Mem.tudw).a;
-                      RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
+                      RdHigh.udw = (Mem.tudw).b;}});
                 //ASI_QUAD_LDD
                 0x24: TwinLoad::ldtx_quad_ldd(
                     {{RdLow.udw = (Mem.tudw).a;
-                      RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
+                      RdHigh.udw = (Mem.tudw).b;}});
                 //ASI_LDTX_REAL
                 0x26: TwinLoad::ldtx_real(
                     {{RdLow.udw = (Mem.tudw).a;
-                      RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
+                      RdHigh.udw = (Mem.tudw).b;}});
                 //ASI_LDTX_N
                 0x27: TwinLoad::ldtx_n(
                     {{RdLow.udw = (Mem.tudw).a;
-                      RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
+                      RdHigh.udw = (Mem.tudw).b;}});
                 //ASI_LDTX_AIUP_L
                 0x2A: TwinLoad::ldtx_aiup_l(
                     {{RdLow.udw = (Mem.tudw).a;
-                      RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
+                      RdHigh.udw = (Mem.tudw).b;}});
                 //ASI_LDTX_AIUS_L
                 0x2B: TwinLoad::ldtx_aius_l(
                     {{RdLow.udw = (Mem.tudw).a;
-                      RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
+                      RdHigh.udw = (Mem.tudw).b;}});
                 //ASI_LDTX_L
                 0x2C: TwinLoad::ldtx_l(
                     {{RdLow.udw = (Mem.tudw).a;
-                      RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
+                      RdHigh.udw = (Mem.tudw).b;}});
                 //ASI_LDTX_REAL_L
                 0x2E: TwinLoad::ldtx_real_l(
                     {{RdLow.udw = (Mem.tudw).a;
-                      RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
+                      RdHigh.udw = (Mem.tudw).b;}});
                 //ASI_LDTX_N_L
                 0x2F: TwinLoad::ldtx_n_l(
                     {{RdLow.udw = (Mem.tudw).a;
-                      RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
+                      RdHigh.udw = (Mem.tudw).b;}});
                 //ASI_LDTX_P
                 0xE2: TwinLoad::ldtx_p(
                     {{RdLow.udw = (Mem.tudw).a;
-                      RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
+                      RdHigh.udw = (Mem.tudw).b;}});
                 //ASI_LDTX_S
                 0xE3: TwinLoad::ldtx_s(
                     {{RdLow.udw = (Mem.tudw).a;
-                      RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
+                      RdHigh.udw = (Mem.tudw).b;}});
                 //ASI_LDTX_PL
                 0xEA: TwinLoad::ldtx_pl(
                     {{RdLow.udw = (Mem.tudw).a;
-                      RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
+                      RdHigh.udw = (Mem.tudw).b;}});
                 //ASI_LDTX_SL
                 0xEB: TwinLoad::ldtx_sl(
                     {{RdLow.udw = (Mem.tudw).a;
-                      RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
+                      RdHigh.udw = (Mem.tudw).b;}});
                 default: ldtwa({{
                         RdLow = (Mem.tuw).a;
-                        RdHigh = (Mem.tuw).b;
-                        }}, {{EXT_ASI}});
+                        RdHigh = (Mem.tuw).b;}});
             }
         }
         format StoreAlt {
-            0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
-            0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
-            0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
+            0x14: stwa({{Mem.uw = Rd;}});
+            0x15: stba({{Mem.ub = Rd;}});
+            0x16: stha({{Mem.uhw = Rd;}});
             0x17: sttwa({{
                       //This temporary needs to be here so that the parser
                       //will correctly identify this instruction as a store.
@@ -1195,25 +1194,25 @@ decode OP default Unknown::unknown()
                       temp.a = RdLow<31:0>;
                       temp.b = RdHigh<31:0>;
                       Mem.tuw = temp;
-                  }}, {{EXT_ASI}});
+                  }});
         }
         format LoadAlt {
-            0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
-            0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
-            0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
-            0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
+            0x18: ldswa({{Rd = (int32_t)Mem.sw;}});
+            0x19: ldsba({{Rd = (int8_t)Mem.sb;}});
+            0x1A: ldsha({{Rd = (int16_t)Mem.shw;}});
+            0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}});
         }
         0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}},
                            {{
                                uint8_t tmp = mem_data;
                                Rd.ub = tmp;
-                           }}, {{EXT_ASI}}, MEM_SWAP);
-        0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
+                           }}, MEM_SWAP);
+        0x1E: StoreAlt::stxa({{Mem.udw = Rd}});
         0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}},
                          {{
                                uint32_t tmp = mem_data;
                                Rd.uw = tmp;
-                         }}, {{EXT_ASI}}, MEM_SWAP);
+                         }}, MEM_SWAP);
 
         format Trap {
             0x20: Load::ldf({{Frds.uw = Mem.uw;}});
@@ -1247,7 +1246,7 @@ decode OP default Unknown::unknown()
             0x26: stqf({{fault = new FpDisabled;}});
             0x27: Store::stdf({{Mem.udw = Frd.udw;}});
             0x2D: Nop::prefetch({{ }});
-            0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}});
+            0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}});
             0x32: ldqfa({{fault = new FpDisabled;}});
             format LoadAlt {
                 0x33: decode EXT_ASI {
@@ -1299,7 +1298,7 @@ decode OP default Unknown::unknown()
                         //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
                         0x1F: FailUnimpl::ldblockf_aiusl();
                         //ASI_BLOCK_PRIMARY
-                        0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}});
+                        0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}});
                         //ASI_BLOCK_SECONDARY
                         0xF1: FailUnimpl::ldblockf_s();
                         //ASI_BLOCK_PRIMARY_LITTLE
@@ -1382,7 +1381,7 @@ decode OP default Unknown::unknown()
                         //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
                         0x1F: FailUnimpl::stblockf_aiusl();
                         //ASI_BLOCK_PRIMARY
-                        0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}});
+                        0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}});
                         //ASI_BLOCK_SECONDARY
                         0xF1: FailUnimpl::stblockf_s();
                         //ASI_BLOCK_PRIMARY_LITTLE
@@ -1419,11 +1418,11 @@ decode OP default Unknown::unknown()
                          {{
                                uint32_t tmp = mem_data;
                                Rd.uw = tmp;
-                         }}, {{EXT_ASI}}, MEM_SWAP_COND);
+                         }}, MEM_SWAP_COND);
             0x3D: Nop::prefetcha({{ }});
             0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2);
                                 Mem.udw = Rd.udw; }},
-                         {{ Rd.udw = mem_data; }}, {{EXT_ASI}}, MEM_SWAP_COND);
+                         {{ Rd.udw = mem_data; }}, MEM_SWAP_COND);
         }
     }
 }
diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa
index aa6c4cdea..e3c043cf3 100644
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -72,22 +72,22 @@ let {{
         return (header_output, decoder_output, exec_output, decode_block)
 }};
 
-def format LoadAlt(code, asi, *opt_flags) {{
+def format LoadAlt(code, *opt_flags) {{
         code = filterDoubles(code)
         (header_output,
          decoder_output,
          exec_output,
          decode_block) = doMemFormat(code, LoadFuncs,
-            AlternateASIPrivFaultCheck, name, Name, asi, opt_flags)
+            AlternateASIPrivFaultCheck, name, Name, "EXT_ASI", opt_flags)
 }};
 
-def format StoreAlt(code, asi, *opt_flags) {{
+def format StoreAlt(code, *opt_flags) {{
         code = filterDoubles(code)
         (header_output,
          decoder_output,
          exec_output,
          decode_block) = doMemFormat(code, StoreFuncs,
-            AlternateASIPrivFaultCheck, name, Name, asi, opt_flags)
+            AlternateASIPrivFaultCheck, name, Name, "EXT_ASI", opt_flags)
 }};
 
 def format Load(code, *opt_flags) {{
@@ -108,12 +108,12 @@ def format Store(code, *opt_flags) {{
              StoreFuncs, '', name, Name, 0, opt_flags)
 }};
 
-def format TwinLoad(code, asi, *opt_flags) {{
+def format TwinLoad(code, *opt_flags) {{
         (header_output,
          decoder_output,
          exec_output,
          decode_block) = doMemFormat(code, LoadFuncs,
             AlternateASIPrivFaultCheck + TwinAlignmentFaultCheck,
-            name, Name, asi, opt_flags)
+            name, Name, "EXT_ASI", opt_flags)
 }};
 
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
index 5d36e5e41..020dc326f 100644
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -273,7 +273,7 @@ def template BlockMemMicroConstructor {{
 
 let {{
 
-    def doBlockMemFormat(code, faultCode, execute, name, Name, asi, opt_flags):
+    def doBlockMemFormat(code, faultCode, execute, name, Name, opt_flags):
         # XXX Need to take care of pstate.hpriv as well. The lower ASIs
         # are split into ones that are available in priv and hpriv, and
         # those that are only available in hpriv
@@ -313,12 +313,12 @@ let {{
                     makeMicroName(name + "Imm", microPc),
                     makeMicroName(Name, microPc),
                     makeMicroName(Name + "Imm", microPc),
-                    asi, opt_flags);
+                    "EXT_ASI", opt_flags);
             faultCode = ''
         return (header_output, decoder_output, exec_output, decode_block)
 }};
 
-def format BlockLoad(code, asi, *opt_flags) {{
+def format BlockLoad(code, *opt_flags) {{
         code = filterDoubles(code)
         # We need to make sure to check the highest priority fault last.
         # That way, if other faults have been detected, they'll be overwritten
@@ -328,10 +328,10 @@ def format BlockLoad(code, asi, *opt_flags) {{
          decoder_output,
          exec_output,
          decode_block) = doBlockMemFormat(code, faultCode,
-             LoadFuncs, name, Name, asi, opt_flags)
+             LoadFuncs, name, Name, opt_flags)
 }};
 
-def format BlockStore(code, asi, *opt_flags) {{
+def format BlockStore(code, *opt_flags) {{
         code = filterDoubles(code)
         # We need to make sure to check the highest priority fault last.
         # That way, if other faults have been detected, they'll be overwritten
@@ -341,5 +341,5 @@ def format BlockStore(code, asi, *opt_flags) {{
          decoder_output,
          exec_output,
          decode_block) = doBlockMemFormat(code, faultCode,
-             StoreFuncs, name, Name, asi, opt_flags)
+             StoreFuncs, name, Name, opt_flags)
 }};
diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa
index dde327f5c..2ebe9aa15 100644
--- a/src/arch/sparc/isa/formats/mem/swap.isa
+++ b/src/arch/sparc/isa/formats/mem/swap.isa
@@ -142,9 +142,9 @@ def format Swap(code, postacc_code, mem_flags, *opt_flags) {{
          ["IsStoreConditional"], postacc_code)
 }};
 
-def format SwapAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{
+def format SwapAlt(code, postacc_code, mem_flags, *opt_flags) {{
     mem_flags = makeList(mem_flags)
-    mem_flags.append(asi)
+    mem_flags.append("EXT_ASI")
     flags = string.join(mem_flags, '|')
     (header_output,
      decoder_output,
@@ -155,7 +155,7 @@ def format SwapAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{
 
 
 let {{
-    def doCasFormat(code, execute, faultCode, name, Name, asi, opt_flags, postacc_code = ''):
+    def doCasFormat(code, execute, faultCode, name, Name, mem_flags, opt_flags, postacc_code = ''):
         addrCalcReg = 'EA = Rs1;'
         iop = InstObjParams(name, Name, 'Mem',
                 {"code": code, "postacc_code" : postacc_code,
@@ -167,15 +167,15 @@ let {{
         microParams = {"code": code, "postacc_code" : postacc_code,
             "ea_code" : addrCalcReg, "fault_check" : faultCode,
             "EA_trunc" : TruncateEA}
-        exec_output = doSplitExecute(execute, name, Name, asi,
+        exec_output = doSplitExecute(execute, name, Name, mem_flags,
                 ["IsStoreConditional"], microParams);
         return (header_output, decoder_output, exec_output, decode_block)
 }};
 
 
-def format CasAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{
+def format CasAlt(code, postacc_code, mem_flags, *opt_flags) {{
     mem_flags = makeList(mem_flags)
-    mem_flags.append(asi)
+    mem_flags.append("EXT_ASI")
     flags = string.join(mem_flags, '|')
     (header_output,
      decoder_output,