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authorAli Saidi <saidi@eecs.umich.edu>2007-02-24 22:10:06 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-02-24 22:10:06 -0500
commitf892608ff7c9898dcbed6dd553632ac2caf4b1ae (patch)
treeb83060a518964e81996a7711b39622e9001d486f /src/arch/sparc/isa
parenta5b73a6e332c3f27ce29346229e1f91c04f53cf9 (diff)
parentcf0e202cbad9823bdd3361164f4b2ee41c4c1501 (diff)
downloadgem5-f892608ff7c9898dcbed6dd553632ac2caf4b1ae.tar.xz
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : a4f80ce975a23ba9858e6bf2dbbfed8897dd1810
Diffstat (limited to 'src/arch/sparc/isa')
-rw-r--r--src/arch/sparc/isa/decoder.isa5
-rw-r--r--src/arch/sparc/isa/operands.isa12
2 files changed, 11 insertions, 6 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 3684cda69..0382aa35e 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1015,6 +1015,11 @@ decode OP default Unknown::unknown()
// we have 7 bits of space here to play with...
0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0);
}}, No_OpClass, IsNonSpeculative);
+ 0x50: m5readfile({{
+ O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2);
+ }}, IsNonSpeculative);
+ 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase());
+ }}, IsNonSpeculative);
0x54: m5panic({{
panic("M5 panic instruction called at pc=%#x.", xc->readPC());
}}, No_OpClass, IsNonSpeculative);
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 82e9407de..092544aab 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -100,12 +100,12 @@ def operands {{
'R1': ('IntReg', 'udw', '1', None, 7),
'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
'R16': ('IntReg', 'udw', '16', None, 9),
- 'O0': ('IntReg', 'udw', '24', 'IsInteger', 10),
- 'O1': ('IntReg', 'udw', '25', 'IsInteger', 11),
- 'O2': ('IntReg', 'udw', '26', 'IsInteger', 12),
- 'O3': ('IntReg', 'udw', '27', 'IsInteger', 13),
- 'O4': ('IntReg', 'udw', '28', 'IsInteger', 14),
- 'O5': ('IntReg', 'udw', '29', 'IsInteger', 15),
+ 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10),
+ 'O1': ('IntReg', 'udw', '9', 'IsInteger', 11),
+ 'O2': ('IntReg', 'udw', '10', 'IsInteger', 12),
+ 'O3': ('IntReg', 'udw', '11', 'IsInteger', 13),
+ 'O4': ('IntReg', 'udw', '12', 'IsInteger', 14),
+ 'O5': ('IntReg', 'udw', '13', 'IsInteger', 15),
# Control registers
# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),