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authorGabe Black <gblack@eecs.umich.edu>2006-10-25 17:58:44 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-10-25 17:58:44 -0400
commit93b3176d4e72813bc64340eb534eb280f68764e1 (patch)
treec5f97f8997671aa14a17d03df4ce7b3beb23435e /src/arch/sparc/isa
parent99d9d40e6c3e4c6c4fbfa3f4475ac3907e6f9d15 (diff)
downloadgem5-93b3176d4e72813bc64340eb534eb280f68764e1.tar.xz
Fixed the priv instruction format.
src/arch/sparc/isa/formats/priv.isa: Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated. src/arch/sparc/isa/operands.isa: Added an Hpstate operand, and adjusted the numbering. --HG-- extra : convert_revision : 4a70862df061aa9e1b9eab125c4c2fc839ac3b5a
Diffstat (limited to 'src/arch/sparc/isa')
-rw-r--r--src/arch/sparc/isa/formats/priv.isa5
-rw-r--r--src/arch/sparc/isa/operands.isa21
2 files changed, 13 insertions, 13 deletions
diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa
index 2a38422a7..04c67d332 100644
--- a/src/arch/sparc/isa/formats/priv.isa
+++ b/src/arch/sparc/isa/formats/priv.isa
@@ -121,15 +121,14 @@ let {{
// Primary format for integer operate instructions:
def format Priv(code, *opt_flags) {{
- checkCode = '''((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>) ||
- ((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)'''
+ checkCode = "!(Pstate<2:2> || Hpstate<2:2>)"
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags + ('IprAccessOp',))
}};
def format HPriv(code, *opt_flags) {{
- checkCode = "((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)"
+ checkCode = "!Hpstate<2:2>"
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags + ('IprAccessOp',))
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index b8b75170b..ba2c38e91 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -95,18 +95,19 @@ def operands {{
'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44),
'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45),
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46),
- 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 47),
+ 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 47),
+ 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 48),
- 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 48),
- 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49),
- 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50),
- 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51),
- 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52),
- 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53),
- 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54),
+ 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 49),
+ 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 50),
+ 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 51),
+ 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 52),
+ 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 53),
+ 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 54),
+ 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 55),
- 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55),
- 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56),
+ 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 56),
+ 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 57),
# Mem gets a large number so it's always last
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)