summaryrefslogtreecommitdiff
path: root/src/arch/sparc/isa
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2006-10-12 17:29:28 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-10-12 17:29:28 -0400
commitb2d9c65db7449f424152b6523a4c653205c4e6b7 (patch)
tree3af117f79999c40e24343e81bbca541566142b34 /src/arch/sparc/isa
parentdd217a9d3fdb9ad5cd2d7c7a3d5eae3d7cd05406 (diff)
downloadgem5-b2d9c65db7449f424152b6523a4c653205c4e6b7.tar.xz
Some support for macro/micro instructions in SPARC.
--HG-- extra : convert_revision : 1f0687d58ab3a4823911a67d8d5c66b27cc211a5
Diffstat (limited to 'src/arch/sparc/isa')
-rw-r--r--src/arch/sparc/isa/formats/micro.isa101
1 files changed, 101 insertions, 0 deletions
diff --git a/src/arch/sparc/isa/formats/micro.isa b/src/arch/sparc/isa/formats/micro.isa
new file mode 100644
index 000000000..867179cfd
--- /dev/null
+++ b/src/arch/sparc/isa/formats/micro.isa
@@ -0,0 +1,101 @@
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+output header {{
+
+ class SparcMacroInst : public SparcStaticInst
+ {
+ protected:
+ const uint32_t numMicroOps;
+
+ //Constructor.
+ SparcMacroInst(const char *mnem, MachInst _machInst,
+ OpClass __opClass, uint32_t _numMicroOps)
+ : SparcStaticInst(mnem, _machInst, __opClass),
+ numMicroOps(_numMicroOps)
+ {
+ assert(numMicroOps);
+ microOps = new StaticInstPtr[numMicroOps];
+ flags[IsMacroOp] = true;
+ }
+
+ ~SparcMacroInst()
+ {
+ delete [] microOps;
+ }
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
+
+ StaticInstPtr * microOps;
+
+ StaticInstPtr fetchMicroOp(MicroPC microPC)
+ {
+ assert(microPC < numMicroOps);
+ return microOps[microPC];
+ }
+ };
+
+ class SparcMicroInst : public SparcStaticInst
+ {
+ protected:
+ //Constructor.
+ SparcMicroInst(const char *mnem,
+ MachInst _machInst, OpClass __opClass)
+ : SparcStaticInst(mnem, _machInst, __opClass)
+ {
+ flags[IsMicroOp] = true;
+ }
+ };
+
+ class SparcDelayedMicroInst : public SparcMicroInst
+ {
+ protected:
+ //Constructor.
+ SparcDelayedMicroInst(const char *mnem,
+ MachInst _machInst, OpClass __opClass)
+ : SparcMicroInst(mnem, _machInst, __opClass)
+ {
+ flags[IsDelayedCommit] = true;
+ }
+ };
+}};
+
+output decoder {{
+
+ std::string SparcMacroInst::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
+
+ printMnemonic(response, mnemonic);
+
+ return response.str();
+ }
+
+}};