summaryrefslogtreecommitdiff
path: root/src/arch/sparc/isa
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2006-07-26 03:40:56 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-07-26 03:40:56 -0400
commite081615cd9d6a41b329fb6a695145152644695b8 (patch)
tree7d84d19e2425dad50af3db1ea7e28cd01db0c679 /src/arch/sparc/isa
parent887e00f18d9ef7d9a293d004617901949aec5b63 (diff)
downloadgem5-e081615cd9d6a41b329fb6a695145152644695b8.tar.xz
Now ignore sigaction
src/arch/sparc/isa/operands.isa: Added the GSR register as a control register --HG-- extra : convert_revision : 11ff4016d5c72468dd2daeba3a6105d4e84220ce
Diffstat (limited to 'src/arch/sparc/isa')
-rw-r--r--src/arch/sparc/isa/operands.isa3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index d250d3672..605816083 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -83,6 +83,7 @@ def operands {{
'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53),
'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54),
- 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55)
+ 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55),
+ 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56)
}};