diff options
| author | Lisa Hsu <hsul@eecs.umich.edu> | 2007-01-19 21:34:21 -0500 |
|---|---|---|
| committer | Lisa Hsu <hsul@eecs.umich.edu> | 2007-01-19 21:34:21 -0500 |
| commit | 01c959aeaf7f4c6e15bae9d8de227b6d2cbb7ae1 (patch) | |
| tree | 158f99a529eccb9c4835a2f544cc4ce59d482ec8 /src/arch/sparc/isa | |
| parent | f1aeaf7ceb44ea6ef7032048a68c74ecedc7685b (diff) | |
| parent | ae0d8d16818e49a16a3c2fa0553acf60514934e6 (diff) | |
| download | gem5-01c959aeaf7f4c6e15bae9d8de227b6d2cbb7ae1.tar.xz | |
Merge zed.eecs.umich.edu:/.automount/zeep/z/saidi/work/m5.newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5
--HG--
extra : convert_revision : 9b8567bb775ed6fcc30096f1ab4cc37058bc7376
Diffstat (limited to 'src/arch/sparc/isa')
| -rw-r--r-- | src/arch/sparc/isa/decoder.isa | 3 | ||||
| -rw-r--r-- | src/arch/sparc/isa/formats/mem/blockmem.isa | 6 |
2 files changed, 7 insertions, 2 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 2e1344a8f..bd1a44342 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1079,6 +1079,9 @@ decode OP default Unknown::unknown() //ASI_LDTX_N_L 0x2F: TwinLoad::ldtx_n_l( {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + //ASI_LDTX_P + 0xE2: TwinLoad::ldtx_p( + {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); default: ldtwa({{ uint64_t val = Mem.udw; RdLow = val<31:0>; diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index 5d05dad03..32421a75f 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -451,6 +451,8 @@ let {{ flag_code = '' if (microPc == 7): flag_code = "flags[IsLastMicroOp] = true;" + elif (microPc == 0): + flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;" else: flag_code = "flags[IsDelayedCommit] = true;" pcedCode = matcher.sub("Frd_%d" % microPc, code) @@ -492,7 +494,7 @@ let {{ flag_code = "flags[IsLastMicroOp] = true;" pcedCode = matcher.sub("RdHigh", code) else: - flag_code = "flags[IsDelayedCommit] = true;" + flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;" pcedCode = matcher.sub("RdLow", code) iop = InstObjParams(name, Name, 'TwinMem', pcedCode, opt_flags, {"ea_code": addrCalcReg, |