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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-01-29 22:54:28 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-01-29 22:54:28 -0500 |
| commit | 4a16ea95c1134d0709670559a96c171b33421db8 (patch) | |
| tree | 4614550a376786053aed3c731256b9f8c8796464 /src/arch/sparc/isa | |
| parent | 1f7db14dd4374d83549db395a6ba477452a25b10 (diff) | |
| download | gem5-4a16ea95c1134d0709670559a96c171b33421db8.tar.xz | |
Fix the Frs?s operands to use single width by default, rather than double width.
--HG--
extra : convert_revision : 36137ee025dc5c79665b041b43bd89505715ca70
Diffstat (limited to 'src/arch/sparc/isa')
| -rw-r--r-- | src/arch/sparc/isa/operands.isa | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 2d1c3d3b9..140055010 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -88,9 +88,9 @@ def operands {{ 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), - 'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11), + 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11), 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), - 'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12), + 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12), 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), |