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authorGabe Black <gblack@eecs.umich.edu>2007-01-30 16:12:47 -0500
committerGabe Black <gblack@eecs.umich.edu>2007-01-30 16:12:47 -0500
commitcf0ba1dfb09c0e16201d963b76078625dc7adca4 (patch)
treecc6ba48cd3aa5a67cbfcd5616aecad91b7c7c04a /src/arch/sparc/isa
parentefb14c585ba1c82c759fccf772368d519d4c02f8 (diff)
parent8bc4925775432f256cfb3be67db6f0d6d7ab6a05 (diff)
downloadgem5-cf0ba1dfb09c0e16201d963b76078625dc7adca4.tar.xz
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 7b332ee4c737206511d26db391117eb1fe5ea290
Diffstat (limited to 'src/arch/sparc/isa')
-rw-r--r--src/arch/sparc/isa/decoder.isa6
-rw-r--r--src/arch/sparc/isa/includes.isa1
2 files changed, 4 insertions, 3 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 8edb51546..81443fecb 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -845,7 +845,7 @@ decode OP default Unknown::unknown()
Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
}});
0x53: FpUnimpl::fcmpq();
- 0x54: fcmpes({{
+ 0x55: fcmpes({{
uint8_t fcc = 0;
if(isnan(Frs1s) || isnan(Frs2s))
fault = new FpExceptionIEEE754;
@@ -858,7 +858,7 @@ decode OP default Unknown::unknown()
firstbit = FCMPCC * 2 + 30;
Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
}});
- 0x55: fcmped({{
+ 0x56: fcmped({{
uint8_t fcc = 0;
if(isnan(Frs1s) || isnan(Frs2s))
fault = new FpExceptionIEEE754;
@@ -871,7 +871,7 @@ decode OP default Unknown::unknown()
firstbit = FCMPCC * 2 + 30;
Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
}});
- 0x56: FpUnimpl::fcmpeq();
+ 0x57: FpUnimpl::fcmpeq();
default: FailUnimpl::fpop2();
}
}
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index 474af3ad9..a6dca9bf1 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -76,5 +76,6 @@ output exec {{
#include "mem/packet_access.hh"
using namespace SparcISA;
+using namespace std;
}};