Implement PR/HPR/ASR for full system

Rip out storage in miscreg file that will never store anything
Add storage and defines for Priv and Hyperpriv registers
Change defines to match the spec register numbers
Change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR.
Change contextval to an int since both global registers and windowed registers are indexed by int in UA2005.
Use bitfields for things that are rarely used in decoder
Instead of decoding ASR/PR/HPR and having a specfic instruction, use a generic instruction instead

Still todo:
Protect rdpr, rdhpr, wrpr, wrhpr with checks that fault in insufficient privs
Deal with signaling interrupts on timer expiration
Deal with writes to softint/PIL generating interrupts how those are vectored to the CPU

Other misc:
Instruction decoding needs major help!

src/arch/sparc/isa/decoder.isa:
    Remove tons of MISCREG_XXXX defines that weren't used and ControlRegs in that were never used. Ones that were used rarely
    changed to bitfields.
src/arch/sparc/isa/formats/integerop.isa:
    These seems like a whole lot of overkill in printing, but i'll leave it the way it is for now. Allow Ccr to be set
    at once
src/arch/sparc/isa/formats/priv.isa:
    PrivTick is handled by miscreg now, don't need a seperate class for it
src/arch/sparc/isa/operands.isa:
    prune the number of control regs down to a reasonable amount
src/arch/sparc/isa_traits.hh:
    Replace 8 defines with 1 and flick some bits
src/arch/sparc/process.cc:
    Better to clean the entire registers that specific bits which leads to indetermanistic behavior.
src/arch/sparc/regfile.hh:
    Rip out storage that will never be backed by anything
    Add storage for Priv and Hyperpriv registers
    change defines to match the spec
    change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR.
    change contextval to an int since both global registers and windowed registers are indexed by int in UA2005.

--HG--
extra : convert_revision : 64276a3ea884eea70112e721f85a515946ded4c2

4 files changed, 120 insertions, 257 deletions

diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index c6e05bf6f..fa8832920 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -44,13 +44,13 @@ decode OP default Unknown::unknown()
             format Branch19
             {
                 0x0: bpcci({{
-                    if(passesCondition(CcrIcc, COND2))
+                    if(passesCondition(Ccr<3:0>, COND2))
                         NNPC = xc->readPC() + disp;
                     else
                         handle_annul
                 }});
                 0x2: bpccx({{
-                    if(passesCondition(CcrXcc, COND2))
+                    if(passesCondition(Ccr<7:4>, COND2))
                         NNPC = xc->readPC() + disp;
                     else
                         handle_annul
@@ -58,7 +58,7 @@ decode OP default Unknown::unknown()
             }
         }
         0x2: Branch22::bicc({{
-            if(passesCondition(CcrIcc, COND2))
+            if(passesCondition(Ccr<3:0>, COND2))
                 NNPC = xc->readPC() + disp;
             else
                 handle_annul
@@ -124,17 +124,17 @@ decode OP default Unknown::unknown()
             0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}});
             0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}});
             0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}});
-            0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + CcrIccC;}});
+            0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
             0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}});
             0x0A: umul({{
                 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
-                YValue = Rd<63:32>;
+                Y = Rd<63:32>;
             }});
             0x0B: smul({{
                 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
-                YValue = Rd.sdw;
+                Y = Rd.sdw;
             }});
-            0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + CcrIccC;}});
+            0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + Ccr<0:0>}});
             0x0D: udivx({{
                 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
                 else Rd.udw = Rs1.udw / Rs2_or_imm13;
@@ -143,7 +143,7 @@ decode OP default Unknown::unknown()
                 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
                 else
                 {
-                    Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
+                    Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
                     if(Rd.udw >> 32 != 0)
                         Rd.udw = 0xFFFFFFFF;
                 }
@@ -153,7 +153,7 @@ decode OP default Unknown::unknown()
                     fault = new DivisionByZero;
                 else
                 {
-                    Rd.udw = ((int64_t)((YValue << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
+                    Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
                     if(Rd.udw<63:31> != 0)
                         Rd.udw = 0x7FFFFFFF;
                     else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
@@ -187,7 +187,7 @@ decode OP default Unknown::unknown()
             0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
             0x18: addccc({{
                 int64_t resTemp, val2 = Rs2_or_imm13;
-                int64_t carryin = CcrIccC;
+                int64_t carryin = Ccr<0:0>;
                 Rd = resTemp = Rs1 + val2 + carryin;}},
                 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
                 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
@@ -198,16 +198,16 @@ decode OP default Unknown::unknown()
             0x1A: umulcc({{
                 uint64_t resTemp;
                 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
-                YValue = resTemp<63:32>;}},
+                Y = resTemp<63:32>;}},
                 {{0}},{{0}},{{0}},{{0}});
             0x1B: smulcc({{
                 int64_t resTemp;
                 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
-                YValue = resTemp<63:32>;}},
+                Y = resTemp<63:32>;}},
                 {{0}},{{0}},{{0}},{{0}});
             0x1C: subccc({{
                 int64_t resTemp, val2 = Rs2_or_imm13;
-                int64_t carryin = CcrIccC;
+                int64_t carryin = Ccr<0:0>;
                 Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
                 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
                 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
@@ -224,7 +224,7 @@ decode OP default Unknown::unknown()
                 if(val2 == 0) fault = new DivisionByZero;
                 else
                 {
-                    resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2;
+                    resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
                     overflow = (resTemp<63:32> != 0);
                     if(overflow) Rd = resTemp = 0xFFFFFFFF;
                     else Rd = resTemp;
@@ -240,7 +240,7 @@ decode OP default Unknown::unknown()
                 if(val2 == 0) fault = new DivisionByZero;
                 else
                 {
-                    Rd = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2;
+                    Rd = resTemp = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
                     overflow = (resTemp<63:31> != 0);
                     underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
                     if(overflow) Rd = resTemp = 0x7FFFFFFF;
@@ -295,12 +295,12 @@ decode OP default Unknown::unknown()
                 int32_t multiplier = Rs1<31:0>;
                 int32_t savedLSB = Rs1<0:>;
                 multiplier = multiplier<31:1> |
-                    ((CcrIccN
-                    ^ CcrIccV) << 32);
-                if(!YValue<0:>)
+                    ((Ccr<3:3>
+                    ^ Ccr<1:1>) << 32);
+                if(!Y<0:>)
                     multiplicand = 0;
                 Rd = resTemp = multiplicand + multiplier;
-                YValue = YValue<31:1> | (savedLSB << 31);}},
+                Y = Y<31:1> | (savedLSB << 31);}},
                 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
                 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
                 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
@@ -321,56 +321,27 @@ decode OP default Unknown::unknown()
                 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
                 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
             }
-            0x28: decode RS1 {
-                0x0: rdy({{Rd = YValue;}});
-                0x2: rdccr({{Rd = Ccr;}});
-                0x3: rdasi({{Rd = Asi;}});
-                0x4: PrivTick::rdtick({{Rd = Tick;}});
-                0x5: rdpc({{Rd = xc->readPC();}});
-                0x6: rdfprs({{Rd = Fprs;}});
-                0xF: decode I {
-                    0x0: Nop::membar({{/*Membar isn't needed yet*/}});
-                    0x1: Nop::stbar({{/*Stbar isn't needed yet*/}});
-                }
-            }
-            0x2A: decode RS1 {
-                format Priv
-                {
-                    0x0: rdprtpc({{
-                        Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl);
-                    }});
-                    0x1: rdprtnpc({{
-                        Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
-                    }});
-                    0x2: rdprtstate({{
-                        Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl);
-                    }});
-                    0x3: rdprtt({{
-                        Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl);
-                    }});
-                    0x4: rdprtick({{Rd = Tick;}});
-                    0x5: rdprtba({{Rd = Tba;}});
-                    0x6: rdprpstate({{Rd = Pstate;}});
-                    0x7: rdprtl({{Rd = Tl;}});
-                    0x8: rdprpil({{Rd = Pil;}});
-                    0x9: rdprcwp({{Rd = Cwp;}});
-                    0xA: rdprcansave({{Rd = Cansave;}});
-                    0xB: rdprcanrestore({{Rd = Canrestore;}});
-                    0xC: rdprcleanwin({{Rd = Cleanwin;}});
-                    0xD: rdprotherwin({{Rd = Otherwin;}});
-                    0xE: rdprwstate({{Rd = Wstate;}});
-                }
-                //The floating point queue isn't implemented right now.
-                0xF: Trap::rdprfq({{fault = new IllegalInstruction;}});
-                0x1F: Priv::rdprver({{Rd = Ver;}});
-            }
+            // XXX might want a format rdipr thing here
+            0x28: rdasr({{
+                Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault);
+            }});
+            0x29: rdhpr({{
+                // XXX Need to protect with format that traps non-priv/priv
+                // access
+                Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
+            }});
+            0x2A: rdpr({{
+                // XXX Need to protect with format that traps non-priv
+                // access
+                Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
+            }});
             0x2B: BasicOperate::flushw({{
                 if(NWindows - 2 - Cansave == 0)
                 {
                     if(Otherwin)
-                        fault = new SpillNOther(WstateOther);
+                        fault = new SpillNOther(Wstate<5:3>);
                     else
-                        fault = new SpillNNormal(WstateNormal);
+                        fault = new SpillNNormal(Wstate<2:0>);
                 }
             }});
             0x2C: decode MOVCC3
@@ -379,13 +350,13 @@ decode OP default Unknown::unknown()
                 0x1: decode CC
                 {
                     0x0: movcci({{
-                        if(passesCondition(CcrIcc, COND4))
+                        if(passesCondition(Ccr<3:0>, COND4))
                             Rd = Rs2_or_imm11;
                         else
                             Rd = Rd;
                     }});
                     0x2: movccx({{
-                        if(passesCondition(CcrXcc, COND4))
+                        if(passesCondition(Ccr<7:4>, COND4))
                             Rd = Rs2_or_imm11;
                         else
                             Rd = Rd;
@@ -419,49 +390,23 @@ decode OP default Unknown::unknown()
                 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
                 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
             }
-            0x30: decode RD {
-                0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}});
-                0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
-                0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
-                0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}});
-                0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}});
-            }
+            0x30: wrasr({{
+                xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
+            }});
             0x31: decode FCN {
                 0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
                 0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
             }
-            0x32: decode RD {
-                format Priv
-                {
-                    0x0: wrprtpc({{
-                        xc->setMiscReg(MISCREG_TPC_BASE + Tl,
-                            Rs1 ^ Rs2_or_imm13);
-                    }});
-                    0x1: wrprtnpc({{
-                        xc->setMiscReg(MISCREG_TNPC_BASE + Tl,
-                            Rs1 ^ Rs2_or_imm13);
-                    }});
-                    0x2: wrprtstate({{
-                        xc->setMiscReg(MISCREG_TSTATE_BASE + Tl,
-                            Rs1 ^ Rs2_or_imm13);
-                    }});
-                    0x3: wrprtt({{
-                        xc->setMiscReg(MISCREG_TT_BASE + Tl,
-                            Rs1 ^ Rs2_or_imm13);
-                    }});
-                    0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
-                    0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
-                    0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
-                    0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}});
-                    0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
-                    0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
-                    0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
-                    0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
-                    0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
-                    0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
-                    0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
-                }
-            }
+            0x32: wrpr({{
+                // XXX Need to protect with format that traps non-priv
+                // access
+                xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
+            }});
+            0x33: wrhpr({{
+                // XXX Need to protect with format that traps non-priv/priv
+                // access
+                xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
+            }});
             0x34: Trap::fpop1({{fault = new FpDisabled;}});
             0x35: Trap::fpop2({{fault = new FpDisabled;}});
             0x38: Branch::jmpl({{
@@ -492,9 +437,9 @@ decode OP default Unknown::unknown()
                     if(Canrestore == 0)
                     {
                         if(Otherwin)
-                            fault = new FillNOther(WstateOther);
+                            fault = new FillNOther(Wstate<5:3>);
                         else
-                            fault = new FillNNormal(WstateNormal);
+                            fault = new FillNNormal(Wstate<2:0>);
                     }
                     else
                     {
@@ -511,7 +456,7 @@ decode OP default Unknown::unknown()
             0x3A: decode CC
             {
                 0x0: Trap::tcci({{
-                    if(passesCondition(CcrIcc, COND2))
+                    if(passesCondition(Ccr<3:0>, COND2))
                     {
                         int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
                         DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
@@ -524,7 +469,7 @@ decode OP default Unknown::unknown()
                     }
                 }});
                 0x2: Trap::tccx({{
-                    if(passesCondition(CcrXcc, COND2))
+                    if(passesCondition(Ccr<7:4>, COND2))
                     {
                         int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
                         DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
@@ -545,9 +490,9 @@ decode OP default Unknown::unknown()
                 if(Cansave == 0)
                 {
                     if(Otherwin)
-                        fault = new SpillNOther(WstateOther);
+                        fault = new SpillNOther(Wstate<5:3>);
                     else
-                        fault = new SpillNNormal(WstateNormal);
+                        fault = new SpillNNormal(Wstate<2:0>);
                     Cwp = (Cwp + 2) % NWindows;
                 }
                 else if(Cleanwin - Canrestore == 0)
@@ -575,9 +520,9 @@ decode OP default Unknown::unknown()
                 if(Canrestore == 0)
                 {
                     if(Otherwin)
-                        fault = new FillNOther(WstateOther);
+                        fault = new FillNOther(Wstate<5:3>);
                     else
-                        fault = new FillNNormal(WstateNormal);
+                        fault = new FillNNormal(Wstate<2:0>);
                 }
                 else
                 {
@@ -594,23 +539,26 @@ decode OP default Unknown::unknown()
                 0x0: Priv::done({{
                     if(Tl == 0)
                         return new IllegalInstruction;
-                    Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl);
-                    Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl);
-                    Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl);
-                    Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl);
-                    NPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
-                    NNPC = NPC + 4;
+
+                    Cwp = Tstate<4:0>;
+                    Pstate = Tstate<20:8>;
+                    Asi = Tstate<31:24>;
+                    Ccr = Tstate<39:32>;
+                    Gl = Tstate<42:40>;
+                    NPC = Tnpc;
+                    NNPC = Tnpc + 4;
                     Tl = Tl - 1;
                 }});
                 0x1: BasicOperate::retry({{
                     if(Tl == 0)
                         return new IllegalInstruction;
-                    Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl);
-                    Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl);
-                    Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl);
-                    Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl);
-                    NPC = xc->readMiscReg(MISCREG_TPC_BASE + Tl);
-                    NNPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
+                    Cwp = Tstate<4:0>;
+                    Pstate = Tstate<20:8>;
+                    Asi = Tstate<31:24>;
+                    Ccr = Tstate<39:32>;
+                    Gl = Tstate<42:40>;
+                    NPC = Tpc;
+                    NNPC = Tnpc + 4;
                     Tl = Tl - 1;
                 }});
             }
diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa
index 1fd87b1d3..1894ce541 100644
--- a/src/arch/sparc/isa/formats/integerop.isa
+++ b/src/arch/sparc/isa/formats/integerop.isa
@@ -316,22 +316,38 @@ let {{
         return (header_output, decoder_output, exec_output, decode_block)
 
     calcCcCode = '''
-        CcrIccN = (Rd >> 31) & 1;
-        CcrIccZ = ((Rd & 0xFFFFFFFF) == 0);
-        CcrXccN = (Rd >> 63) & 1;
-        CcrXccZ = (Rd == 0);
-        CcrIccV = %(ivValue)s;
-        CcrIccC = %(icValue)s;
-        CcrXccV = %(xvValue)s;
-        CcrXccC = %(xcValue)s;
-        DPRINTF(Sparc, "in = %%d\\n", CcrIccN);
-        DPRINTF(Sparc, "iz = %%d\\n", CcrIccZ);
-        DPRINTF(Sparc, "xn = %%d\\n", CcrXccN);
-        DPRINTF(Sparc, "xz = %%d\\n", CcrXccZ);
-        DPRINTF(Sparc, "iv = %%d\\n", CcrIccV);
-        DPRINTF(Sparc, "ic = %%d\\n", CcrIccC);
-        DPRINTF(Sparc, "xv = %%d\\n", CcrXccV);
-        DPRINTF(Sparc, "xc = %%d\\n", CcrXccC);
+        uint8_t tmp_ccriccc;
+        uint8_t tmp_ccriccv;
+        uint8_t tmp_ccriccz;
+        uint8_t tmp_ccriccn;
+        uint8_t tmp_ccrxccc;
+        uint8_t tmp_ccrxccv;
+        uint8_t tmp_ccrxccz;
+        uint8_t tmp_ccrxccn;
+
+        tmp_ccriccn = (Rd >> 31) & 1;
+        tmp_ccriccz = ((Rd & 0xFFFFFFFF) == 0);
+        tmp_ccrxccn = (Rd >> 63) & 1;
+        tmp_ccrxccz = (Rd == 0);
+        tmp_ccriccv = %(ivValue)s & 1;
+        tmp_ccriccc = %(icValue)s & 1;
+        tmp_ccrxccv = %(xvValue)s & 1;
+        tmp_ccrxccc = %(xcValue)s & 1;
+
+        Ccr =  tmp_ccriccc | tmp_ccriccv << 1 |
+               tmp_ccriccz << 2 | tmp_ccriccn << 3|
+               tmp_ccrxccc << 4 | tmp_ccrxccv << 5|
+               tmp_ccrxccz << 6| tmp_ccrxccn << 7;
+
+
+        DPRINTF(Sparc, "in = %%d\\n", (uint16_t)tmp_ccriccn);
+        DPRINTF(Sparc, "iz = %%d\\n", (uint16_t)tmp_ccriccz);
+        DPRINTF(Sparc, "xn = %%d\\n", (uint16_t)tmp_ccrxccn);
+        DPRINTF(Sparc, "xz = %%d\\n", (uint16_t)tmp_ccrxccz);
+        DPRINTF(Sparc, "iv = %%d\\n", (uint16_t)tmp_ccriccv);
+        DPRINTF(Sparc, "ic = %%d\\n", (uint16_t)tmp_ccriccc);
+        DPRINTF(Sparc, "xv = %%d\\n", (uint16_t)tmp_ccrxccv);
+        DPRINTF(Sparc, "xc = %%d\\n", (uint16_t)tmp_ccrxccc);
         '''
 }};
 
diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa
index a8de22c0e..7df59d736 100644
--- a/src/arch/sparc/isa/formats/priv.isa
+++ b/src/arch/sparc/isa/formats/priv.isa
@@ -51,23 +51,6 @@ output header {{
         };
 
         /**
-         * Base class for user mode "tick" access.
-         */
-        class PrivTick : public SparcStaticInst
-        {
-          protected:
-            // Constructor
-            PrivTick(const char *mnem, ExtMachInst _machInst,
-                    OpClass __opClass) :
-                SparcStaticInst(mnem, _machInst, __opClass)
-            {
-            }
-
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
-        };
-
-        /**
          * Base class for privelege mode operations with immediates.
          */
         class PrivImm : public Priv
@@ -83,21 +66,6 @@ output header {{
             int32_t imm;
         };
 
-        /**
-         * Base class for user mode "tick" access with immediates.
-         */
-        class PrivTickImm : public PrivTick
-        {
-          protected:
-            // Constructor
-            PrivTickImm(const char *mnem, ExtMachInst _machInst,
-                    OpClass __opClass) :
-                PrivTick(mnem, _machInst, __opClass), imm(SIMM13)
-            {
-            }
-
-            int32_t imm;
-        };
 }};
 
 output decoder {{
@@ -106,12 +74,6 @@ output decoder {{
         {
                 return "Privileged Instruction";
         }
-
-        std::string PrivTick::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-                return "Regular access to Tick";
-        }
 }};
 
 def template PrivExecute {{
@@ -154,16 +116,10 @@ let {{
 
 // Primary format for integer operate instructions:
 def format Priv(code, *opt_flags) {{
-        checkCode = "(!PstatePriv)"
+        checkCode = "((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>)"
         (header_output, decoder_output,
          exec_output, decode_block) = doPrivFormat(code,
              checkCode, name, Name, opt_flags)
 }};
 
-// Primary format for integer operate instructions:
-def format PrivTick(code, *opt_flags) {{
-        checkCode = "(!PstatePriv && TickNpt)"
-        (header_output, decoder_output,
-         exec_output, decode_block) = doPrivFormat(code,
-             checkCode, name, Name, opt_flags)
-}};
+
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index a89034e30..9e5c783e8 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -63,83 +63,26 @@ def operands {{
     'R1':  		('IntReg', 'udw', '1', None, 7),
     'R15': 		('IntReg', 'udw', '15', 'IsInteger', 8),
     'R16': 		('IntReg', 'udw', '16', None, 9),
+
     # Control registers
-    'Pstate':		('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
-    'PstateAg':		('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2),
-    'PstateIe':		('ControlReg', 'udw', 'MISCREG_PSTATE_IE', None, 3),
-    'PstatePriv':	('ControlReg', 'udw', 'MISCREG_PSTATE_PRIV', None, 4),
-    'PstateAm':		('ControlReg', 'udw', 'MISCREG_PSTATE_AM', None, 5),
-    'PstatePef':	('ControlReg', 'udw', 'MISCREG_PSTATE_PEF', None, 6),
-    'PstateRed':	('ControlReg', 'udw', 'MISCREG_PSTATE_RED', None, 7),
-    'PstateMm':		('ControlReg', 'udw', 'MISCREG_PSTATE_MM', None, 8),
-    'PstateTle':	('ControlReg', 'udw', 'MISCREG_PSTATE_TLE', None, 9),
-    'PstateCle':	('ControlReg', 'udw', 'MISCREG_PSTATE_CLE', None, 10),
-    'Tba':		('ControlReg', 'udw', 'MISCREG_TBA', None, 11),
     'Y':		('ControlReg', 'udw', 'MISCREG_Y', None, 12),
-    'YValue':		('ControlReg', 'udw', 'MISCREG_Y_VALUE', None, 13),
-    'Pil':		('ControlReg', 'udw', 'MISCREG_PIL', None, 14),
-    'Cwp':		('ControlReg', 'udw', 'MISCREG_CWP', None, 15),
-    #'Tt':		('ControlReg', 'udw', 'MISCREG_TT_BASE + tl', None, 16),
     'Ccr':		('ControlReg', 'udw', 'MISCREG_CCR', None, 17),
-    'CcrIcc':		('ControlReg', 'udw', 'MISCREG_CCR_ICC', None, 18),
-    'CcrIccC':		('ControlReg', 'udw', 'MISCREG_CCR_ICC_C', None, 19),
-    'CcrIccV':		('ControlReg', 'udw', 'MISCREG_CCR_ICC_V', None, 20),
-    'CcrIccZ':		('ControlReg', 'udw', 'MISCREG_CCR_ICC_Z', None, 21),
-    'CcrIccN':		('ControlReg', 'udw', 'MISCREG_CCR_ICC_N', None, 22),
-    'CcrXcc':		('ControlReg', 'udw', 'MISCREG_CCR_XCC', None, 23),
-    'CcrXccC':		('ControlReg', 'udw', 'MISCREG_CCR_XCC_C', None, 22),
-    'CcrXccV':		('ControlReg', 'udw', 'MISCREG_CCR_XCC_V', None, 23),
-    'CcrXccZ':		('ControlReg', 'udw', 'MISCREG_CCR_XCC_Z', None, 24),
-    'CcrXccN':		('ControlReg', 'udw', 'MISCREG_CCR_XCC_N', None, 25),
     'Asi':		('ControlReg', 'udw', 'MISCREG_ASI', None, 26),
+
+    'Tpc':		('ControlReg', 'udw', 'MISCREG_TPC', None, 28),
+    'Tnpc':		('ControlReg', 'udw', 'MISCREG_TNPC', None, 28),
+    'Tstate':		('ControlReg', 'udw', 'MISCREG_TSTATE', None, 28),
+    'Pstate':		('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
     'Tl':		('ControlReg', 'udw', 'MISCREG_TL', None, 27),
-    #'Tpc':		('ControlReg', 'udw', 'MISCREG_TPC', None, 28),
-    'Tick':		('ControlReg', 'udw', 'MISCREG_TICK', None, 29),
-    'TickCounter':	('ControlReg', 'udw', 'MISCREG_TICK_COUNTER', None, 32),
-    'TickNpt':		('ControlReg', 'udw', 'MISCREG_TICK_NPT', None, 33),
+
+    'Cwp':		('ControlReg', 'udw', 'MISCREG_CWP', None, 15),
     'Cansave':		('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 34),
     'Canrestore':	('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 35),
-    'Otherwin':		('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36),
     'Cleanwin':		('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 37),
+    'Otherwin':		('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36),
     'Wstate':		('ControlReg', 'udw', 'MISCREG_WSTATE', None, 38),
-    'WstateNormal':	('ControlReg', 'udw', 'MISCREG_WSTATE_NORMAL', None,39),
-    'WstateOther':	('ControlReg', 'udw', 'MISCREG_WSTATE_OTHER', None, 40),
-    'Ver':		('ControlReg', 'udw', 'MISCREG_VER', None, 41),
-    'VerMaxwin':	('ControlReg', 'udw', 'MISCREG_VER_MAXWIN', None, 42),
-    'VerMaxtl':		('ControlReg', 'udw', 'MISCREG_VER_MAXTL', None, 43),
-    'VerMask':		('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 44),
-    'VerImpl':		('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 45),
-    'VerManuf':		('ControlReg', 'udw', 'MISCREG_VER_MANUF', None, 46),
-    'Fsr':		('ControlReg', 'udw', 'MISCREG_FSR', None, 47),
-    'FsrCexc':		('ControlReg', 'udw', 'MISCREG_FSR_CEXC', None, 48),
-    'FsrCexcNxc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NXC', None, 49),
-    'FsrCexcDzc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_DZC', None, 50),
-    'FsrCexcUfc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_UFC', None, 51),
-    'FsrCexcOfc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_OFC', None, 52),
-    'FsrCexcNvc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NVC', None, 53),
-    'FsrAexc':		('ControlReg', 'udw', 'MISCREG_FSR_AEXC', None, 54),
-    'FsrAexcNxc':	('ControlReg', 'udw', 'MISCREG_FSR_AEXC_NXC', None, 55),
-    'FsrAexcDzc':	('ControlReg', 'udw', 'MISCREG_FSR_AEXC_DZC', None, 56),
-    'FsrAexcUfc':	('ControlReg', 'udw', 'MISCREG_FSR_AEXC_UFC', None, 57),
-    'FsrAexcOfc':	('ControlReg', 'udw', 'MISCREG_FSR_AEXC_OFC', None, 58),
-    'FsrAexcNvc':	('ControlReg', 'udw', 'MISCREC_FSR_AEXC_NVC', None, 59),
-    'FsrFcc0':		('ControlReg', 'udw', 'MISCREG_FSR_FCC0', None, 60),
-    'FsrQne':		('ControlReg', 'udw', 'MISCREG_FSR_QNE', None, 61),
-    'FsrFtt':		('ControlReg', 'udw', 'MISCREG_FSR_FTT', None, 62),
-    'FsrVer':		('ControlReg', 'udw', 'MISCREG_FSR_VER', None, 63),
-    'FsrNs':		('ControlReg', 'udw', 'MISCREG_FSR_NS', None, 64),
-    'FsrTem':		('ControlReg', 'udw', 'MISCREG_FSR_TEM', None, 65),
-    'FsrTemNxm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_NXM', None, 66),
-    'FsrTemDzm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_DZM', None, 67),
-    'FsrTemUfm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_UFM', None, 68),
-    'FsrTemOfm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_OFM', None, 69),
-    'FsrTemNvm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_NVM', None, 70),
-    'FsrRd':		('ControlReg', 'udw', 'MISCREG_FSR_RD', None, 71),
-    'FsrFcc1':		('ControlReg', 'udw', 'MISCREG_FSR_FCC1', None, 72),
-    'FsrFcc2':		('ControlReg', 'udw', 'MISCREG_FSR_FCC2', None, 73),
-    'FsrFcc3':		('ControlReg', 'udw', 'MISCREG_FSR_FCC3', None, 74),
-    'Fprs':		('ControlReg', 'udw', 'MISCREG_FPRS', None, 75),
-    'FprsDl':		('ControlReg', 'udw', 'MISCREG_FPRS_DL', None, 76),
-    'FprsDu':		('ControlReg', 'udw', 'MISCREG_FPRS_DU', None, 77),
-    'FprsFef':		('ControlReg', 'udw', 'MISCREG_FPRS_FEF', None, 78)
+    'Gl':               ('ControlReg', 'udw', 'MISCREG_GL', None, 12),
+
+    'Fsr':		('ControlReg', 'udw', 'MISCREG_FSR', None, 47)
+
 }};