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authorGabe Black <gblack@eecs.umich.edu>2006-10-27 02:34:26 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-10-27 02:34:26 -0400
commitf985b752d352b1f4bb253ad2372955f4caed72ea (patch)
tree209a3fc534dc357aa0217bffba70127cc7767874 /src/arch/sparc/isa
parent2f30c2b4c982b61b393a2888c022fbeac3225d59 (diff)
parentca34c62bf96b66fdb1aefc3b08cad8d969ee6bc9 (diff)
downloadgem5-f985b752d352b1f4bb253ad2372955f4caed72ea.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem --HG-- extra : convert_revision : ec35a9276ae21e0b9fe820bd700c020e4440a350
Diffstat (limited to 'src/arch/sparc/isa')
-rw-r--r--src/arch/sparc/isa/bitfields.isa2
-rw-r--r--src/arch/sparc/isa/decoder.isa75
-rw-r--r--src/arch/sparc/isa/formats/priv.isa5
-rw-r--r--src/arch/sparc/isa/operands.isa21
4 files changed, 57 insertions, 46 deletions
diff --git a/src/arch/sparc/isa/bitfields.isa b/src/arch/sparc/isa/bitfields.isa
index 372f5c4ef..7e884866c 100644
--- a/src/arch/sparc/isa/bitfields.isa
+++ b/src/arch/sparc/isa/bitfields.isa
@@ -50,7 +50,7 @@ def bitfield D16LO <13:0>;
def bitfield DISP19 <18:0>;
def bitfield DISP22 <21:0>;
def bitfield DISP30 <29:0>;
-def bitfield FCN <29:26>;
+def bitfield FCN <29:25>;
def bitfield I <13>;
def bitfield IMM_ASI <12:5>;
def bitfield IMM22 <21:0>;
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 45d3616d9..dc7597e5e 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -357,13 +357,9 @@ decode OP default Unknown::unknown()
}});
}
0x29: HPriv::rdhpr({{
- // XXX Need to protect with format that traps non-priv/priv
- // access
Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
}});
0x2A: Priv::rdpr({{
- // XXX Need to protect with format that traps non-priv
- // access
Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
}});
0x2B: BasicOperate::flushw({{
@@ -425,18 +421,34 @@ decode OP default Unknown::unknown()
xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
}});
0x31: decode FCN {
- 0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
- 0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
+ 0x0: Priv::saved({{
+ assert(Cansave < NWindows - 2);
+ assert(Otherwin || Canrestore);
+ Cansave = Cansave + 1;
+ if(Otherwin == 0)
+ Canrestore = Canrestore - 1;
+ else
+ Otherwin = Otherwin - 1;
+ }});
+ 0x1: BasicOperate::restored({{
+ assert(Cansave || Otherwin);
+ assert(Canrestore < NWindows - 2);
+ Canrestore = Canrestore + 1;
+ if(Otherwin == 0)
+ Cansave = Cansave - 1;
+ else
+ Otherwin = Otherwin - 1;
+ }});
}
0x32: Priv::wrpr({{
// XXX Need to protect with format that traps non-priv
// access
- fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
+ xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
}});
0x33: HPriv::wrhpr({{
// XXX Need to protect with format that traps non-priv/priv
// access
- fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
+ xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
}});
0x34: decode OPF{
format BasicOperate{
@@ -684,10 +696,6 @@ decode OP default Unknown::unknown()
NNPC = target;
if(fault == NoFault)
{
- //CWP should be set directly so that it always happens
- //Also, this will allow writing to the new window and
- //reading from the old one
- Cwp = (Cwp - 1 + NWindows) % NWindows;
if(Canrestore == 0)
{
if(Otherwin)
@@ -697,14 +705,17 @@ decode OP default Unknown::unknown()
}
else
{
- Rd = Rs1 + Rs2_or_imm13;
+ //CWP should be set directly so that it always happens
+ //Also, this will allow writing to the new window and
+ //reading from the old one
+ Cwp = (Cwp - 1 + NWindows) % NWindows;
Cansave = Cansave + 1;
Canrestore = Canrestore - 1;
+ //This is here to make sure the CWP is written
+ //no matter what. This ensures that the results
+ //are written in the new window as well.
+ xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
}
- //This is here to make sure the CWP is written
- //no matter what. This ensures that the results
- //are written in the new window as well.
- xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
}
}});
0x3A: decode CC
@@ -747,11 +758,11 @@ decode OP default Unknown::unknown()
fault = new SpillNOther(Wstate<5:3>);
else
fault = new SpillNNormal(Wstate<2:0>);
- Cwp = (Cwp + 2) % NWindows;
+ //Cwp = (Cwp + 2) % NWindows;
}
else if(Cleanwin - Canrestore == 0)
{
- Cwp = (Cwp + 1) % NWindows;
+ //Cwp = (Cwp + 1) % NWindows;
fault = new CleanWindow;
}
else
@@ -760,17 +771,13 @@ decode OP default Unknown::unknown()
Rd = Rs1 + Rs2_or_imm13;
Cansave = Cansave - 1;
Canrestore = Canrestore + 1;
+ //This is here to make sure the CWP is written
+ //no matter what. This ensures that the results
+ //are written in the new window as well.
+ xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
}
- //This is here to make sure the CWP is written
- //no matter what. This ensures that the results
- //are written in the new window as well.
- xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
}});
0x3D: restore({{
- //CWP should be set directly so that it always happens
- //Also, this will allow writing to the new window and
- //reading from the old one
- Cwp = (Cwp - 1 + NWindows) % NWindows;
if(Canrestore == 0)
{
if(Otherwin)
@@ -780,14 +787,18 @@ decode OP default Unknown::unknown()
}
else
{
+ //CWP should be set directly so that it always happens
+ //Also, this will allow writing to the new window and
+ //reading from the old one
+ Cwp = (Cwp - 1 + NWindows) % NWindows;
Rd = Rs1 + Rs2_or_imm13;
Cansave = Cansave + 1;
Canrestore = Canrestore - 1;
+ //This is here to make sure the CWP is written
+ //no matter what. This ensures that the results
+ //are written in the new window as well.
+ xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
}
- //This is here to make sure the CWP is written
- //no matter what. This ensures that the results
- //are written in the new window as well.
- xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
}});
0x3E: decode FCN {
0x0: Priv::done({{
@@ -812,7 +823,7 @@ decode OP default Unknown::unknown()
Ccr = Tstate<39:32>;
Gl = Tstate<42:40>;
NPC = Tpc;
- NNPC = Tnpc + 4;
+ NNPC = Tnpc;
Tl = Tl - 1;
}});
}
diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa
index 2a38422a7..04c67d332 100644
--- a/src/arch/sparc/isa/formats/priv.isa
+++ b/src/arch/sparc/isa/formats/priv.isa
@@ -121,15 +121,14 @@ let {{
// Primary format for integer operate instructions:
def format Priv(code, *opt_flags) {{
- checkCode = '''((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>) ||
- ((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)'''
+ checkCode = "!(Pstate<2:2> || Hpstate<2:2>)"
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags + ('IprAccessOp',))
}};
def format HPriv(code, *opt_flags) {{
- checkCode = "((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)"
+ checkCode = "!Hpstate<2:2>"
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags + ('IprAccessOp',))
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index b8b75170b..ba2c38e91 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -95,18 +95,19 @@ def operands {{
'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44),
'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45),
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46),
- 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 47),
+ 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 47),
+ 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 48),
- 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 48),
- 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49),
- 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50),
- 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51),
- 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52),
- 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53),
- 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54),
+ 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 49),
+ 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 50),
+ 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 51),
+ 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 52),
+ 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 53),
+ 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 54),
+ 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 55),
- 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55),
- 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56),
+ 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 56),
+ 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 57),
# Mem gets a large number so it's always last
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)