arch: ISA parser additions of vector registers

Reiley's update :) of the isa parser definitions. My addition of the
vector element operand concept for the ISA parser. Nathanael's modification
creating a hierarchy between vector registers and its constituencies to the
isa parser.

Some fixes/updates on top to consider instructions as vectors instead of
floating when they use the VectorRF. Some counters added to all the
models to keep faithful counts.

Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2706
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 5 insertions, 0 deletions

diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index b517d462c..4b61c940c 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -578,6 +578,11 @@ output exec {{
             return NoFault;
         }
     }
+    static inline Fault
+    checkVecEnableFault(CPU_EXEC_CONTEXT *xc)
+    {
+        return std::make_shared<VecDisabled>();
+    }
 }};