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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-02 22:34:51 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-02 22:34:51 -0500 |
| commit | 4e8d2d1593475008b926829e6944a59963166079 (patch) | |
| tree | 42ff01c4146f48c23179de7d2b01f4e6bdbe97d7 /src/arch/sparc/isa | |
| parent | d8ada247f4fb107e7dc530ceb96a624d46c8ed9a (diff) | |
| download | gem5-4e8d2d1593475008b926829e6944a59963166079.tar.xz | |
make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads
src/arch/isa_parser.py:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/operands.isa:
src/base/bigint.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/mem/packet_access.hh:
make ldtw(a) Twin 32 bit load work correctly
--HG--
extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42
Diffstat (limited to 'src/arch/sparc/isa')
| -rw-r--r-- | src/arch/sparc/isa/decoder.isa | 10 | ||||
| -rw-r--r-- | src/arch/sparc/isa/operands.isa | 3 |
2 files changed, 6 insertions, 7 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 36b9d1caa..2e85e1274 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1160,9 +1160,8 @@ decode OP default Unknown::unknown() 0x01: ldub({{Rd = Mem.ub;}}); 0x02: lduh({{Rd = Mem.uhw;}}); 0x03: ldtw({{ - uint64_t val = Mem.udw; - RdLow = val<31:0>; - RdHigh = val<63:32>; + RdLow = (Mem.tuw).a; + RdHigh = (Mem.tuw).b; }}); } format Store { @@ -1250,9 +1249,8 @@ decode OP default Unknown::unknown() {{RdLow.udw = (Mem.tudw).a; RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); default: ldtwa({{ - uint64_t val = Mem.udw; - RdLow = val<31:0>; - RdHigh = val<63:32>; + RdLow = (Mem.tuw).a; + RdHigh = (Mem.tuw).b; }}, {{EXT_ASI}}); } } diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 092544aab..038919bd1 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -37,7 +37,8 @@ def operand_types {{ 'uw' : ('unsigned int', 32), 'sdw' : ('signed int', 64), 'udw' : ('unsigned int', 64), - 'tudw' : ('twin int', 64), + 'tudw' : ('twin64 int', 64), + 'tuw' : ('twin32 int', 32), 'sf' : ('float', 32), 'df' : ('float', 64), 'qf' : ('float', 128) |