arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700

4 files changed, 31 insertions, 30 deletions

diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index 90013ae42..4a4293e50 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -105,12 +105,12 @@ output header {{
             std::string generateDisassembly(Addr pc,
                 const SymbolTable *symtab) const;
 
-            void printReg(std::ostream &os, int reg) const;
+            void printReg(std::ostream &os, RegId reg) const;
             void printSrcReg(std::ostream &os, int reg) const;
             void printDestReg(std::ostream &os, int reg) const;
 
             void printRegArray(std::ostream &os,
-                const RegIndex indexArray[], int num) const;
+                const RegId indexArray[], int num) const;
 
             void advancePC(SparcISA::PCState &pcState) const;
         };
@@ -251,7 +251,7 @@ output decoder {{
         }
 
         void SparcStaticInst::printRegArray(std::ostream &os,
-            const RegIndex indexArray[], int num) const
+            const RegId indexArray[], int num) const
         {
             if (num <= 0)
                 return;
@@ -283,35 +283,36 @@ output decoder {{
         }
 
         void
-        SparcStaticInst::printReg(std::ostream &os, int reg) const
+        SparcStaticInst::printReg(std::ostream &os, RegId reg) const
         {
             const int MaxGlobal = 8;
             const int MaxOutput = 16;
             const int MaxLocal = 24;
             const int MaxInput = 32;
             const int MaxMicroReg = 40;
-            if (reg < FP_Reg_Base) {
+            RegIndex reg_idx = reg.regIdx;
+            if (reg.regClass == IntRegClass) {
                 // If we used a register from the next or previous window,
                 // take out the offset.
-                while (reg >= MaxMicroReg)
-                    reg -= MaxMicroReg;
-                if (reg == FramePointerReg)
+                while (reg_idx >= MaxMicroReg)
+                    reg_idx -= MaxMicroReg;
+                if (reg_idx == FramePointerReg)
                     ccprintf(os, "%%fp");
-                else if (reg == StackPointerReg)
+                else if (reg_idx == StackPointerReg)
                     ccprintf(os, "%%sp");
-                else if (reg < MaxGlobal)
-                    ccprintf(os, "%%g%d", reg);
-                else if (reg < MaxOutput)
-                    ccprintf(os, "%%o%d", reg - MaxGlobal);
-                else if (reg < MaxLocal)
-                    ccprintf(os, "%%l%d", reg - MaxOutput);
-                else if (reg < MaxInput)
-                    ccprintf(os, "%%i%d", reg - MaxLocal);
-                else if (reg < MaxMicroReg)
-                    ccprintf(os, "%%u%d", reg - MaxInput);
+                else if (reg_idx < MaxGlobal)
+                    ccprintf(os, "%%g%d", reg_idx);
+                else if (reg_idx < MaxOutput)
+                    ccprintf(os, "%%o%d", reg_idx - MaxGlobal);
+                else if (reg_idx < MaxLocal)
+                    ccprintf(os, "%%l%d", reg_idx - MaxOutput);
+                else if (reg_idx < MaxInput)
+                    ccprintf(os, "%%i%d", reg_idx - MaxLocal);
+                else if (reg_idx < MaxMicroReg)
+                    ccprintf(os, "%%u%d", reg_idx - MaxInput);
                 // The fake int regs that are really control regs
                 else {
-                    switch (reg - MaxMicroReg) {
+                    switch (reg_idx - MaxMicroReg) {
                       case 1:
                         ccprintf(os, "%%y");
                         break;
@@ -335,10 +336,10 @@ output decoder {{
                         break;
                     }
                 }
-            } else if (reg < Misc_Reg_Base) {
-                ccprintf(os, "%%f%d", reg - FP_Reg_Base);
+            } else if (reg.regClass == FloatRegClass) {
+                ccprintf(os, "%%f%d", reg_idx);
             } else {
-                switch (reg - Misc_Reg_Base) {
+                switch (reg_idx) {
                   case MISCREG_ASI:
                     ccprintf(os, "%%asi");
                     break;
@@ -430,7 +431,7 @@ output decoder {{
                     ccprintf(os, "%%fsr");
                     break;
                   default:
-                    ccprintf(os, "%%ctrl%d", reg - Misc_Reg_Base);
+                    ccprintf(os, "%%ctrl%d", reg_idx);
                 }
             }
         }
diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa
index 355bbf393..585dfcced 100644
--- a/src/arch/sparc/isa/formats/integerop.isa
+++ b/src/arch/sparc/isa/formats/integerop.isa
@@ -155,7 +155,7 @@ output decoder {{
         IntOp::printPseudoOps(std::ostream &os, Addr pc,
                 const SymbolTable *symbab) const
         {
-            if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) {
+            if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0].regIdx == 0) {
                 printMnemonic(os, "mov");
                 printSrcReg(os, 1);
                 ccprintf(os, ", ");
@@ -170,7 +170,7 @@ output decoder {{
                 const SymbolTable *symbab) const
         {
             if (!std::strcmp(mnemonic, "or")) {
-                if (_numSrcRegs > 0 && _srcRegIdx[0] == 0) {
+                if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx == 0) {
                     if (imm == 0) {
                         printMnemonic(os, "clr");
                     } else {
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 0a07f55dd..9b3132e40 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -84,7 +84,7 @@ output decoder {{
                 ccprintf(response, ", ");
             }
             ccprintf(response, "[");
-            if (_srcRegIdx[!store ? 0 : 1] != 0) {
+            if (_srcRegIdx[!store ? 0 : 1].regIdx != 0) {
                 printSrcReg(response, !store ? 0 : 1);
                 ccprintf(response, " + ");
             }
@@ -111,7 +111,7 @@ output decoder {{
                 ccprintf(response, ", ");
             }
             ccprintf(response, "[");
-            if (_srcRegIdx[!save ? 0 : 1] != 0) {
+            if (_srcRegIdx[!save ? 0 : 1].regIdx != 0) {
                 printReg(response, _srcRegIdx[!save ? 0 : 1]);
                 ccprintf(response, " + ");
             }
diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa
index 24b553fe3..f5e1a0826 100644
--- a/src/arch/sparc/isa/formats/priv.isa
+++ b/src/arch/sparc/isa/formats/priv.isa
@@ -155,7 +155,7 @@ output decoder {{
             ccprintf(response, " ");
             // If the first reg is %g0, don't print it.
             // This improves readability
-            if (_srcRegIdx[0] != 0) {
+            if (_srcRegIdx[0].regIdx != 0) {
                 printSrcReg(response, 0);
                 ccprintf(response, ", ");
             }
@@ -175,7 +175,7 @@ output decoder {{
             ccprintf(response, " ");
             // If the first reg is %g0, don't print it.
             // This improves readability
-            if (_srcRegIdx[0] != 0) {
+            if (_srcRegIdx[0].regIdx != 0) {
                 printSrcReg(response, 0);
                 ccprintf(response, ", ");
             }