fix twinx loads a little bit

bugfixes and demap implementation in tlb
ignore some more differencs for one cycle

src/arch/sparc/isa/formats/mem/blockmem.isa:
    twinx has 2 micro-ops
src/arch/sparc/isa/formats/mem/util.isa:
    fix the fault check for twinx
src/arch/sparc/tlb.cc:
    tlb bugfixes and write demapping code
src/cpu/exetrace.cc:
    don't halt on a couple more instruction (ldx, stx) when things differ
    beacuse of the way tlb faults are handled in legion.

--HG--
extra : convert_revision : 1e156dead6ebd58b257213625ed63c3793ef4b71

2 files changed, 3 insertions, 3 deletions

diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
index 8bbbdc1da..5d05dad03 100644
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -101,7 +101,7 @@ output header {{
             // We make the assumption that all block memory operations
             // Will take 8 instructions to execute
             TwinMem(const char *mnem, ExtMachInst _machInst) :
-                SparcMacroInst(mnem, _machInst, No_OpClass, 8)
+                SparcMacroInst(mnem, _machInst, No_OpClass, 2)
             {}
         };
 
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 3f9146c21..b6e0945b7 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -285,9 +285,9 @@ let {{
             fault = new MemAddressNotAligned;
     '''
     TwinAlignmentFaultCheck = '''
-        if(RD & 0xe)
+        if(RD & 0x1)
             fault = new IllegalInstruction;
-        else if(EA & 0x1f)
+        else if(EA & 0xf)
             fault = new MemAddressNotAligned;
     '''
     # XXX Need to take care of pstate.hpriv as well. The lower ASIs