Merge ktlim@zizzer:/bk/newmem

into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

--HG--
extra : convert_revision : 88fa7ae5cc32be068787ee381fae9d8de0e9bd0f

1 files changed, 9 insertions, 6 deletions

diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 6d5aa4251..46a0ebbfb 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -57,14 +57,17 @@ namespace SparcISA
     //This makes sure the big endian versions of certain functions are used.
     using namespace BigEndianGuest;
 
-    // Alpha Does NOT have a delay slot
+    // SPARC has a delay slot
     #define ISA_HAS_DELAY_SLOT 1
 
-    //TODO this needs to be a SPARC Noop
-    // Alpha UNOP (ldq_u r31,0(r0))
-    const MachInst NoopMachInst = 0x2ffe0000;
+    // SPARC NOP (sethi %(hi(0), g0)
+    const MachInst NoopMachInst = 0x01000000;
 
-    const int NumIntRegs = 32;
+    const int NumRegularIntRegs = 32;
+    const int NumMicroIntRegs = 1;
+    const int NumIntRegs =
+        NumRegularIntRegs +
+        NumMicroIntRegs;
     const int NumFloatRegs = 64;
     const int NumMiscRegs = 40;
 
@@ -87,7 +90,7 @@ namespace SparcISA
     const int MaxPGL = 2;
 
     // NWINDOWS - number of register windows, can be 3 to 32
-    const int NWindows = 32;
+    const int NWindows = 8;
 
     // semantically meaningful register indices
     const int ZeroReg = 0;	// architecturally meaningful