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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-04-21 08:17:36 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-04-21 08:17:36 -0700 |
| commit | 52b6764f31cab46204d5fdf6d0191428a8408bb1 (patch) | |
| tree | 8c0ae8d04cb0e3a2b6b2fc3a7c6a0be5a44d3927 /src/arch/sparc/isa_traits.hh | |
| parent | b0e9654f8621729400ba627ed8c9bd0bf3833f7a (diff) | |
| download | gem5-52b6764f31cab46204d5fdf6d0191428a8408bb1.tar.xz | |
syscall: Resolve conflicts between m5threads and Gabe's recent SE changes.
Diffstat (limited to 'src/arch/sparc/isa_traits.hh')
| -rw-r--r-- | src/arch/sparc/isa_traits.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 501f2f990..9833057a2 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -69,6 +69,7 @@ namespace SparcISA const int ZeroReg = 0; // architecturally meaningful // the rest of these depend on the ABI const int ReturnAddressReg = 31; // post call, precall is 15 + const int ReturnValueReg = 8; // Post return, 24 is pre-return. const int StackPointerReg = 14; const int FramePointerReg = 30; |