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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-12-13 22:04:36 -0800 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-12-13 22:04:36 -0800 |
| commit | d172e1576a9d8fd422d881c8f72a9c5cc4b6b9a6 (patch) | |
| tree | 93bfd057e44d9c450d0c1103d668de9ec9dda8fc /src/arch/sparc/isa_traits.hh | |
| parent | 98bb1c62b31e988f81d9fc03cf14aca25fd008db (diff) | |
| download | gem5-d172e1576a9d8fd422d881c8f72a9c5cc4b6b9a6.tar.xz | |
Split CachePort class into CpuSidePort and MemSidePort
and push those into derived Cache template class to
eliminate a few layers of virtual functions and
conditionals ("if (isCpuSide) { ... }" etc.).
--HG--
extra : convert_revision : cb1b88246c95b36aa0cf26d534127d3714ddb774
Diffstat (limited to 'src/arch/sparc/isa_traits.hh')
0 files changed, 0 insertions, 0 deletions