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authorGabe Black <gblack@eecs.umich.edu>2006-11-22 23:49:44 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-11-22 23:49:44 -0500
commit758c78065167ab58d63754827971a149c51282b9 (patch)
tree81b1a14749946072bf9d579937f19a8da744670b /src/arch/sparc/isa_traits.hh
parentf85082e0a00ff7ba9caf79a58f41c6c4e351cd9d (diff)
downloadgem5-758c78065167ab58d63754827971a149c51282b9.tar.xz
Moved some constants from isa_traits.hh to the reg file headers.
--HG-- extra : convert_revision : 378b2d9791e6282539900a2261ad2275d726b4be
Diffstat (limited to 'src/arch/sparc/isa_traits.hh')
-rw-r--r--src/arch/sparc/isa_traits.hh45
1 files changed, 3 insertions, 42 deletions
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 1433ba3f8..008f45bcd 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -32,16 +32,9 @@
#define __ARCH_SPARC_ISA_TRAITS_HH__
#include "arch/sparc/types.hh"
-#include "base/misc.hh"
+#include "arch/sparc/sparc_traits.hh"
#include "config/full_system.hh"
-#include "sim/host.hh"
-class ThreadContext;
-class FastCPU;
-//class FullCPU;
-class Checkpoint;
-
-class StaticInst;
class StaticInstPtr;
namespace BigEndianGuest {}
@@ -63,32 +56,12 @@ namespace SparcISA
// SPARC NOP (sethi %(hi(0), g0)
const MachInst NoopMachInst = 0x01000000;
- const int NumRegularIntRegs = 32;
- const int NumMicroIntRegs = 1;
- const int NumIntRegs =
- NumRegularIntRegs +
- NumMicroIntRegs;
- const int NumFloatRegs = 64;
- const int NumMiscRegs = 40;
-
// These enumerate all the registers for dependence tracking.
enum DependenceTags {
- // 0..31 are the integer regs 0..31
- // 32..95 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
- FP_Base_DepTag = NumIntRegs,
- Ctrl_Base_DepTag = NumIntRegs + NumMicroIntRegs + NumFloatRegs,
+ FP_Base_DepTag = 33,
+ Ctrl_Base_DepTag = 97,
};
-
- // MAXTL - maximum trap level
- const int MaxPTL = 2;
- const int MaxTL = 6;
- const int MaxGL = 3;
- const int MaxPGL = 2;
-
- // NWINDOWS - number of register windows, can be 3 to 32
- const int NWindows = 8;
-
// semantically meaningful register indices
const int ZeroReg = 0; // architecturally meaningful
// the rest of these depend on the ABI
@@ -120,19 +93,7 @@ namespace SparcISA
const int BranchPredAddrShiftAmt = 2;
- const int MachineBytes = 8;
- const int WordBytes = 4;
- const int HalfwordBytes = 2;
- const int ByteBytes = 1;
-
- void serialize(std::ostream & os);
-
- void unserialize(Checkpoint *cp, const std::string &section);
-
StaticInstPtr decodeInst(ExtMachInst);
-
- // return a no-op instruction... used for instruction fetch faults
- extern const MachInst NoopMachInst;
}
#endif // __ARCH_SPARC_ISA_TRAITS_HH__