diff options
author | Ali Saidi <saidi@eecs.umich.edu> | 2006-11-23 01:42:57 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-11-23 01:42:57 -0500 |
commit | 271b9a5435ac26c836774b25ad1fa68e2351d25a (patch) | |
tree | 4e411c5f80fdc2030f147777b9a5860ad32fdb6e /src/arch/sparc/isa_traits.hh | |
parent | ef5b842247ec3f13cc7c321324130eab0f636052 (diff) | |
download | gem5-271b9a5435ac26c836774b25ad1fa68e2351d25a.tar.xz |
first cut at a sparc tlb
src/arch/sparc/SConscript:
Add code to serialize/unserialze tlb entries
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
update asi names for how they're listed in the supplement
add asis
add more asi functions
src/arch/sparc/isa_traits.hh:
move the interrupt stuff and some basic address space stuff into isa traits
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
add mmu registers to tlb
get rid of implicit asi stuff... the tlb will handle it
src/arch/sparc/regfile.hh:
make isnt/dataAsid return ints not asis
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
first cut at sparc tlb
src/arch/sparc/vtophys.hh:
pagatable nedes to be included here
src/mem/request.hh:
add asi and if the request is a memory mapped register to the requset object
src/sim/host.hh:
fix incorrect definition of LL
--HG--
extra : convert_revision : 6c85cd1681c62c8cd8eab04f70b1f15a034b0aa3
Diffstat (limited to 'src/arch/sparc/isa_traits.hh')
-rw-r--r-- | src/arch/sparc/isa_traits.hh | 29 |
1 files changed, 25 insertions, 4 deletions
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 1433ba3f8..109fdfae7 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -26,6 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Gabe Black + * Ali Saidi */ #ifndef __ARCH_SPARC_ISA_TRAITS_HH__ @@ -46,10 +47,6 @@ class StaticInstPtr; namespace BigEndianGuest {} -#if FULL_SYSTEM -#include "arch/sparc/isa_fullsys_traits.hh" -#endif - namespace SparcISA { class RegFile; @@ -133,6 +130,30 @@ namespace SparcISA // return a no-op instruction... used for instruction fetch faults extern const MachInst NoopMachInst; + +#if FULL_SYSTEM + ////////// Interrupt Stuff /////////// + enum InterruptLevels + { + INTLEVEL_MIN = 1, + INTLEVEL_MAX = 15, + + NumInterruptLevels = INTLEVEL_MAX - INTLEVEL_MIN + }; + + // I don't know what it's for, so I don't + // know what SPARC's value should be + // For loading... XXX This maybe could be USegEnd?? --ali + const Addr LoadAddrMask = ULL(0xffffffffff); + + /////////// TLB Stuff //////////// + const Addr StartVAddrHole = ULL(0x0000800000000000); + const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF); + const Addr VAddrAMask = ULL(0xFFFFFFFF); + const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF); + const Addr BytesInPageMask = ULL(0x1FFF); + +#endif } #endif // __ARCH_SPARC_ISA_TRAITS_HH__ |