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authorGabe Black <gblack@eecs.umich.edu>2007-08-26 20:24:18 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-08-26 20:24:18 -0700
commit537239b278f7b8171d2eb09ef7f99c332266c48f (patch)
tree31984b63cc542f0a57ca96262477575ab0130c09 /src/arch/sparc/isa_traits.hh
parentf738afb865cd82487d6300259d6e87fb50660d2a (diff)
downloadgem5-537239b278f7b8171d2eb09ef7f99c332266c48f.tar.xz
Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
--HG-- extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
Diffstat (limited to 'src/arch/sparc/isa_traits.hh')
-rw-r--r--src/arch/sparc/isa_traits.hh12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 0edbdec4b..4f3d20606 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -98,12 +98,6 @@ namespace SparcISA
StaticInstPtr decodeInst(ExtMachInst);
-#if FULL_SYSTEM
- // I don't know what it's for, so I don't
- // know what SPARC's value should be
- // For loading... XXX This maybe could be USegEnd?? --ali
- const Addr LoadAddrMask = ULL(0xffffffffff);
-
/////////// TLB Stuff ////////////
const Addr StartVAddrHole = ULL(0x0000800000000000);
const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
@@ -111,6 +105,12 @@ namespace SparcISA
const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
const Addr BytesInPageMask = ULL(0x1FFF);
+#if FULL_SYSTEM
+ // I don't know what it's for, so I don't
+ // know what SPARC's value should be
+ // For loading... XXX This maybe could be USegEnd?? --ali
+ const Addr LoadAddrMask = ULL(0xffffffffff);
+
enum InterruptTypes
{
IT_TRAP_LEVEL_ZERO,