Merge zizzer:/bk/sparcfs

into  zower.eecs.umich.edu:/eecshome/m5/newmemmid

src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.hh:
    hand merge

--HG--
extra : convert_revision : 34f50dc5e6e22096cb2c08b5888f2b0fcd418f3e

1 files changed, 217 insertions, 36 deletions

diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index 7b0939c29..d2164155f 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -102,8 +102,32 @@ void MiscRegFile::clear()
     //This is set this way in Legion for some reason
     strandStatusReg = 0x50000;
     fsr = 0;
-    implicitInstAsi = ASI_PRIMARY;
-    implicitDataAsi = ASI_PRIMARY;
+
+    priContext = 0;
+    secContext = 0;
+    partId = 0;
+    lsuCtrlReg = 0;
+
+    iTlbC0TsbPs0 = 0;
+    iTlbC0TsbPs1 = 0;
+    iTlbC0Config = 0;
+    iTlbCXTsbPs0 = 0;
+    iTlbCXTsbPs1 = 0;
+    iTlbCXConfig = 0;
+    iTlbSfsr = 0;
+    iTlbTagAccess = 0;
+
+    dTlbC0TsbPs0 = 0;
+    dTlbC0TsbPs1 = 0;
+    dTlbC0Config = 0;
+    dTlbCXTsbPs0 = 0;
+    dTlbCXTsbPs1 = 0;
+    dTlbCXConfig = 0;
+    dTlbSfsr = 0;
+    dTlbSfar = 0;
+    dTlbTagAccess = 0;
+
+    memset(scratchPad, 0, sizeof(scratchPad));
 }
 
 MiscReg MiscRegFile::readReg(int miscReg)
@@ -187,6 +211,69 @@ MiscReg MiscRegFile::readReg(int miscReg)
         /** Floating Point Status Register */
         case MISCREG_FSR:
           return fsr;
+
+        case MISCREG_MMU_P_CONTEXT:
+          return priContext;
+        case MISCREG_MMU_S_CONTEXT:
+          return secContext;
+        case MISCREG_MMU_PART_ID:
+          return partId;
+        case MISCREG_MMU_LSU_CTRL:
+          return lsuCtrlReg;
+
+        case MISCREG_MMU_ITLB_C0_TSB_PS0:
+          return iTlbC0TsbPs0;
+        case MISCREG_MMU_ITLB_C0_TSB_PS1:
+          return iTlbC0TsbPs1;
+        case MISCREG_MMU_ITLB_C0_CONFIG:
+          return iTlbC0Config;
+        case MISCREG_MMU_ITLB_CX_TSB_PS0:
+          return iTlbCXTsbPs0;
+        case MISCREG_MMU_ITLB_CX_TSB_PS1:
+          return iTlbCXTsbPs1;
+        case MISCREG_MMU_ITLB_CX_CONFIG:
+          return iTlbCXConfig;
+        case MISCREG_MMU_ITLB_SFSR:
+          return iTlbSfsr;
+        case MISCREG_MMU_ITLB_TAG_ACCESS:
+          return iTlbTagAccess;
+
+        case MISCREG_MMU_DTLB_C0_TSB_PS0:
+          return dTlbC0TsbPs0;
+        case MISCREG_MMU_DTLB_C0_TSB_PS1:
+          return dTlbC0TsbPs1;
+        case MISCREG_MMU_DTLB_C0_CONFIG:
+          return dTlbC0Config;
+        case MISCREG_MMU_DTLB_CX_TSB_PS0:
+          return dTlbCXTsbPs0;
+        case MISCREG_MMU_DTLB_CX_TSB_PS1:
+          return dTlbCXTsbPs1;
+        case MISCREG_MMU_DTLB_CX_CONFIG:
+          return dTlbCXConfig;
+        case MISCREG_MMU_DTLB_SFSR:
+          return dTlbSfsr;
+        case MISCREG_MMU_DTLB_SFAR:
+          return dTlbSfar;
+        case MISCREG_MMU_DTLB_TAG_ACCESS:
+          return dTlbTagAccess;
+
+        case MISCREG_SCRATCHPAD_R0:
+          return scratchPad[0];
+        case MISCREG_SCRATCHPAD_R1:
+          return scratchPad[1];
+        case MISCREG_SCRATCHPAD_R2:
+          return scratchPad[2];
+        case MISCREG_SCRATCHPAD_R3:
+          return scratchPad[3];
+        case MISCREG_SCRATCHPAD_R4:
+          return scratchPad[4];
+        case MISCREG_SCRATCHPAD_R5:
+          return scratchPad[5];
+        case MISCREG_SCRATCHPAD_R6:
+          return scratchPad[6];
+        case MISCREG_SCRATCHPAD_R7:
+          return scratchPad[7];
+
         default:
           panic("Miscellaneous register %d not implemented\n", miscReg);
     }
@@ -333,35 +420,95 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
         case MISCREG_FSR:
           fsr = val;
           break;
+
+        case MISCREG_MMU_P_CONTEXT:
+          priContext = val;
+          break;
+        case MISCREG_MMU_S_CONTEXT:
+          secContext = val;
+          break;
+        case MISCREG_MMU_PART_ID:
+          partId = val;
+          break;
+        case MISCREG_MMU_LSU_CTRL:
+          lsuCtrlReg = val;
+          break;
+
+        case MISCREG_MMU_ITLB_C0_TSB_PS0:
+          iTlbC0TsbPs0 = val;
+          break;
+        case MISCREG_MMU_ITLB_C0_TSB_PS1:
+          iTlbC0TsbPs1 = val;
+          break;
+        case MISCREG_MMU_ITLB_C0_CONFIG:
+          iTlbC0Config = val;
+          break;
+        case MISCREG_MMU_ITLB_CX_TSB_PS0:
+          iTlbCXTsbPs0 = val;
+          break;
+        case MISCREG_MMU_ITLB_CX_TSB_PS1:
+          iTlbCXTsbPs1 = val;
+          break;
+        case MISCREG_MMU_ITLB_CX_CONFIG:
+          iTlbCXConfig = val;
+          break;
+        case MISCREG_MMU_ITLB_SFSR:
+          iTlbSfsr = val;
+          break;
+        case MISCREG_MMU_ITLB_TAG_ACCESS:
+          iTlbTagAccess = val;
+          break;
+
+        case MISCREG_MMU_DTLB_C0_TSB_PS0:
+          dTlbC0TsbPs0 = val;
+          break;
+        case MISCREG_MMU_DTLB_C0_TSB_PS1:
+          dTlbC0TsbPs1 = val;
+          break;
+        case MISCREG_MMU_DTLB_C0_CONFIG:
+          dTlbC0Config = val;
+          break;
+        case MISCREG_MMU_DTLB_CX_TSB_PS0:
+          dTlbCXTsbPs0 = val;
+          break;
+        case MISCREG_MMU_DTLB_CX_TSB_PS1:
+          dTlbCXTsbPs1 = val;
+          break;
+        case MISCREG_MMU_DTLB_CX_CONFIG:
+          dTlbCXConfig = val;
+          break;
+        case MISCREG_MMU_DTLB_SFSR:
+          dTlbSfsr = val;
+          break;
+        case MISCREG_MMU_DTLB_SFAR:
+          dTlbSfar = val;
+          break;
+        case MISCREG_MMU_DTLB_TAG_ACCESS:
+          dTlbTagAccess = val;
+          break;
+
+        case MISCREG_SCRATCHPAD_R0:
+           scratchPad[0] = val;
+        case MISCREG_SCRATCHPAD_R1:
+           scratchPad[1] = val;
+        case MISCREG_SCRATCHPAD_R2:
+           scratchPad[2] = val;
+        case MISCREG_SCRATCHPAD_R3:
+           scratchPad[3] = val;
+        case MISCREG_SCRATCHPAD_R4:
+           scratchPad[4] = val;
+        case MISCREG_SCRATCHPAD_R5:
+           scratchPad[5] = val;
+        case MISCREG_SCRATCHPAD_R6:
+           scratchPad[6] = val;
+        case MISCREG_SCRATCHPAD_R7:
+           scratchPad[7] = val;
+
         default:
           panic("Miscellaneous register %d not implemented\n", miscReg);
     }
 }
 
-inline void MiscRegFile::setImplicitAsis()
-{
-    //The spec seems to use trap level to indicate the privilege level of the
-    //processor. It's unclear whether the implicit ASIs should directly depend
-    //on the trap level, or if they should really be based on the privelege
-    //bits
-    if(tl == 0)
-    {
-        implicitInstAsi = implicitDataAsi =
-            (pstate & (1 << 9)) ? ASI_PRIMARY_LITTLE : ASI_PRIMARY;
-    }
-    else if(tl <= MaxPTL)
-    {
-        implicitInstAsi = ASI_NUCLEUS;
-        implicitDataAsi = (pstate & (1 << 9)) ? ASI_NUCLEUS_LITTLE : ASI_NUCLEUS;
-    }
-    else
-    {
-        //This is supposed to force physical addresses to match the spec.
-        //It might not because of context values and partition values.
-        implicitInstAsi = implicitDataAsi = ASI_REAL;
-    }
-}
-
 void MiscRegFile::setRegWithEffect(int miscReg,
         const MiscReg &val, ThreadContext * tc)
 {
@@ -383,11 +530,9 @@ void MiscRegFile::setRegWithEffect(int miscReg,
           break;
         case MISCREG_PSTATE:
           pstate = val & PSTATE_MASK;
-          setImplicitAsis();
           return;
         case MISCREG_TL:
           tl = val;
-          setImplicitAsis();
           return;
         case MISCREG_CWP:
           tc->changeRegFileContext(CONTEXT_CWP, val);
@@ -490,8 +635,28 @@ void MiscRegFile::serialize(std::ostream & os)
     SERIALIZE_ARRAY(htstate, MaxTL);
     SERIALIZE_SCALAR(htba);
     SERIALIZE_SCALAR(hstick_cmpr);
-    SERIALIZE_SCALAR((int)implicitInstAsi);
-    SERIALIZE_SCALAR((int)implicitDataAsi);
+    SERIALIZE_SCALAR(strandStatusReg);
+    SERIALIZE_SCALAR(priContext);
+    SERIALIZE_SCALAR(secContext);
+    SERIALIZE_SCALAR(partId);
+    SERIALIZE_SCALAR(lsuCtrlReg);
+    SERIALIZE_SCALAR(iTlbC0TsbPs0);
+    SERIALIZE_SCALAR(iTlbC0TsbPs1);
+    SERIALIZE_SCALAR(iTlbC0Config);
+    SERIALIZE_SCALAR(iTlbCXTsbPs0);
+    SERIALIZE_SCALAR(iTlbCXTsbPs1);
+    SERIALIZE_SCALAR(iTlbCXConfig);
+    SERIALIZE_SCALAR(iTlbSfsr);
+    SERIALIZE_SCALAR(iTlbTagAccess);
+    SERIALIZE_SCALAR(dTlbC0TsbPs0);
+    SERIALIZE_SCALAR(dTlbC0TsbPs1);
+    SERIALIZE_SCALAR(dTlbC0Config);
+    SERIALIZE_SCALAR(dTlbCXTsbPs0);
+    SERIALIZE_SCALAR(dTlbCXTsbPs1);
+    SERIALIZE_SCALAR(dTlbSfsr);
+    SERIALIZE_SCALAR(dTlbSfar);
+    SERIALIZE_SCALAR(dTlbTagAccess);
+    SERIALIZE_ARRAY(scratchPad,8);
 }
 
 void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
@@ -521,12 +686,28 @@ void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
     UNSERIALIZE_ARRAY(htstate, MaxTL);
     UNSERIALIZE_SCALAR(htba);
     UNSERIALIZE_SCALAR(hstick_cmpr);
-    int temp;
-    UNSERIALIZE_SCALAR(temp);
-    implicitInstAsi = (ASI)temp;
-    UNSERIALIZE_SCALAR(temp);
-    implicitDataAsi = (ASI)temp;
-}
+    UNSERIALIZE_SCALAR(strandStatusReg);
+    UNSERIALIZE_SCALAR(priContext);
+    UNSERIALIZE_SCALAR(secContext);
+    UNSERIALIZE_SCALAR(partId);
+    UNSERIALIZE_SCALAR(lsuCtrlReg);
+    UNSERIALIZE_SCALAR(iTlbC0TsbPs0);
+    UNSERIALIZE_SCALAR(iTlbC0TsbPs1);
+    UNSERIALIZE_SCALAR(iTlbC0Config);
+    UNSERIALIZE_SCALAR(iTlbCXTsbPs0);
+    UNSERIALIZE_SCALAR(iTlbCXTsbPs1);
+    UNSERIALIZE_SCALAR(iTlbCXConfig);
+    UNSERIALIZE_SCALAR(iTlbSfsr);
+    UNSERIALIZE_SCALAR(iTlbTagAccess);
+    UNSERIALIZE_SCALAR(dTlbC0TsbPs0);
+    UNSERIALIZE_SCALAR(dTlbC0TsbPs1);
+    UNSERIALIZE_SCALAR(dTlbC0Config);
+    UNSERIALIZE_SCALAR(dTlbCXTsbPs0);
+    UNSERIALIZE_SCALAR(dTlbCXTsbPs1);
+    UNSERIALIZE_SCALAR(dTlbSfsr);
+    UNSERIALIZE_SCALAR(dTlbSfar);
+    UNSERIALIZE_SCALAR(dTlbTagAccess);
+    UNSERIALIZE_ARRAY(scratchPad,8);}
 
 #if FULL_SYSTEM
 void