diff options
| author | Lisa Hsu <hsul@eecs.umich.edu> | 2007-01-11 09:48:15 -0500 |
|---|---|---|
| committer | Lisa Hsu <hsul@eecs.umich.edu> | 2007-01-11 09:48:15 -0500 |
| commit | 5c9cbdbb4597a3ba6908a41c1dc459c25626e514 (patch) | |
| tree | 1bc33a9661ecc1dd4538ee10183ef809488830f2 /src/arch/sparc/miscregfile.cc | |
| parent | 9f75c1c58f8352a8625f035c151ebcf6ce95b908 (diff) | |
| parent | 42535f5f53ad2515cd4b8e617e4a2322aecac547 (diff) | |
| download | gem5-5c9cbdbb4597a3ba6908a41c1dc459c25626e514.tar.xz | |
Merge zed.eecs.umich.edu:/z/hsul/work/sparc/ali.m5
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
src/arch/sparc/ua2005.cc:
hand merge between ali and me.
--HG--
extra : convert_revision : 810d63fb484ab26fc30f8130ef32390ba149b267
Diffstat (limited to 'src/arch/sparc/miscregfile.cc')
| -rw-r--r-- | src/arch/sparc/miscregfile.cc | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index c58a1fd09..50f510289 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -326,12 +326,8 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) | mbits(tick,63,63); case MISCREG_FPRS: - warn("FPRS register read and FPU stuff not really implemented\n"); // in legion if fp is enabled du and dl are set - if (fprs & 0x4) - return 0x7; - else - return 0; + return fprs | 0x3; case MISCREG_PCR: case MISCREG_PIC: panic("Performance Instrumentation not impl\n"); @@ -389,7 +385,6 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val) asi = val; break; case MISCREG_FPRS: - warn("FPU not really implemented writing %#X to FPRS\n", val); fprs = val; break; case MISCREG_TICK: @@ -612,6 +607,8 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val) void MiscRegFile::setRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc) { + MiscReg new_val = val; + switch (miscReg) { case MISCREG_STICK: case MISCREG_TICK: @@ -634,7 +631,8 @@ void MiscRegFile::setRegWithEffect(int miscReg, tl = val; return; case MISCREG_CWP: - tc->changeRegFileContext(CONTEXT_CWP, val); + new_val = val > NWindows ? NWindows - 1 : val; + tc->changeRegFileContext(CONTEXT_CWP, new_val); break; case MISCREG_GL: tc->changeRegFileContext(CONTEXT_GLOBALS, val); @@ -671,7 +669,7 @@ void MiscRegFile::setRegWithEffect(int miscReg, panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val); #endif } - setReg(miscReg, val); + setReg(miscReg, new_val); } void MiscRegFile::serialize(std::ostream & os) |