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authorGabe Black <gblack@eecs.umich.edu>2006-11-20 18:08:50 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-11-20 18:08:50 -0500
commitb4a31cb8b554056fa48ad3986c4f011b8d312306 (patch)
treedc6cae0d0284d6f0648a838708ff28e357a65185 /src/arch/sparc/miscregfile.cc
parenta0287c1e2d3fb3842703222763fef9bad4a61c9d (diff)
downloadgem5-b4a31cb8b554056fa48ad3986c4f011b8d312306.tar.xz
Make sure only real bits of pstate can be set.
--HG-- extra : convert_revision : 8707bbed2aeb80613f86503e92b63853767adaa9
Diffstat (limited to 'src/arch/sparc/miscregfile.cc')
-rw-r--r--src/arch/sparc/miscregfile.cc9
1 files changed, 7 insertions, 2 deletions
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index 8ca3d66f9..a60288984 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -62,6 +62,11 @@ string SparcISA::getMiscRegName(RegIndex index)
return miscRegName[index];
}
+enum RegMask
+{
+ PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
+};
+
void MiscRegFile::reset()
{
y = 0;
@@ -275,7 +280,7 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
tba = val & ULL(~0x7FFF);
break;
case MISCREG_PSTATE:
- pstate = val;
+ pstate = (val & PSTATE_MASK);
break;
case MISCREG_TL:
tl = val;
@@ -377,7 +382,7 @@ void MiscRegFile::setRegWithEffect(int miscReg,
//Set up performance counting based on pcr value
break;
case MISCREG_PSTATE:
- pstate = val;
+ pstate = val & PSTATE_MASK;
setImplicitAsis();
return;
case MISCREG_TL: