diff options
author | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-14 19:01:21 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-14 19:01:21 -0500 |
commit | fa4293af33e48e9e9374dada5a8efcd0c41554a4 (patch) | |
tree | 9d80f37f65b63bb8e8edcfd85e3b3664c0a873ae /src/arch/sparc/miscregfile.cc | |
parent | 139519ef87ceb4ab6c7f0246dd98b002e7bde3f9 (diff) | |
download | gem5-fa4293af33e48e9e9374dada5a8efcd0c41554a4.tar.xz |
flesh out twinx asis
fix TICK register reads
reduce the number of readmiscreg accesses,
implement tsb pointer stuff
src/arch/sparc/asi.cc:
flesh out twinx asis
src/arch/sparc/miscregfile.cc:
fix TICK register reads
src/arch/sparc/tlb.cc:
reduce the number of readmiscreg accesses,
implement tsb pointer stuff
--HG--
extra : convert_revision : 1995c3b04b7743c6122cbf8ded7c4d5de48fa3c8
Diffstat (limited to 'src/arch/sparc/miscregfile.cc')
-rw-r--r-- | src/arch/sparc/miscregfile.cc | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index dbcd91925..5bc11aae6 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -314,16 +314,17 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) { switch (miscReg) { // tick and stick are aliased to each other in niagra - case MISCREG_TICK: + // well store the tick data in stick and the interrupt bit in tick case MISCREG_STICK: + case MISCREG_TICK: case MISCREG_PRIVTICK: // I'm not sure why legion ignores the lowest two bits, but we'll go // with it // change from curCycle() to instCount() until we're done with legion - DPRINTFN("Instruction Count when STICK read: %#X\n", - tc->getCpuPtr()->instCount()); - return mbits(tc->getCpuPtr()->instCount() - (tick & - mask(63)),62,2) | mbits(tick,63,63) ; + DPRINTFN("Instruction Count when TICK read: %#X stick=%#X\n", + tc->getCpuPtr()->instCount(), stick); + return mbits(tc->getCpuPtr()->instCount() + (int32_t)stick,62,2) | + mbits(tick,63,63); case MISCREG_FPRS: warn("FPRS register read and FPU stuff not really implemented\n"); return fprs; @@ -601,13 +602,14 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val) void MiscRegFile::setRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc) { - const uint64_t Bit64 = (1ULL << 63); switch (miscReg) { case MISCREG_STICK: case MISCREG_TICK: - // change from curCycle() to instCount() until we're done with legion - tick = tc->getCpuPtr()->instCount() - val & ~Bit64; - tick |= val & Bit64; + // stick and tick are same thing on niagra + // use stick for offset and tick for holding intrrupt bit + stick = mbits(val,62,0) - tc->getCpuPtr()->instCount(); + tick = mbits(val,63,63); + DPRINTFN("Writing TICK=%#X\n", val); break; case MISCREG_FPRS: //Configure the fpu based on the fprs |