diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-05 01:55:02 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-05 01:55:02 -0500 |
commit | 12c5bd2305a83c65d068686ec2d6588bde769805 (patch) | |
tree | 4ec41b3570c2a0d137e18b2ca38318c4639599ae /src/arch/sparc/miscregfile.cc | |
parent | f2daf210f1cac2dd0a102b9d796fb700d4be92d1 (diff) | |
download | gem5-12c5bd2305a83c65d068686ec2d6588bde769805.tar.xz |
Move the SyscallReturn class into sim/syscallreturn.hh. Also move some miscregs into the integer register file so they get renamed.
src/arch/alpha/syscallreturn.hh:
src/arch/mips/syscallreturn.hh:
src/sim/syscallreturn.hh:
Move the SyscallReturn class into sim/syscallreturn.hh
src/arch/sparc/faults.cc:
src/arch/sparc/isa/operands.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
src/arch/sparc/process.cc:
src/arch/sparc/sparc_traits.hh:
Move some miscregs into the integer register file so they get renamed.
--HG--
extra : convert_revision : df5b94fa1e7fdca34816084e0a423d6fdf86c79b
Diffstat (limited to 'src/arch/sparc/miscregfile.cc')
-rw-r--r-- | src/arch/sparc/miscregfile.cc | 76 |
1 files changed, 38 insertions, 38 deletions
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index 7b0939c29..50a4f4871 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -50,12 +50,12 @@ class Checkpoint; string SparcISA::getMiscRegName(RegIndex index) { static::string miscRegName[NumMiscRegs] = - {"y", "ccr", "asi", "tick", "fprs", "pcr", "pic", + {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic", "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr", "stick", "stick_cmpr", "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl", - "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", - "wstate", "gl", + "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin", + "wstate",*/ "gl", "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg", "hstick_cmpr", "fsr"}; @@ -109,10 +109,10 @@ void MiscRegFile::clear() MiscReg MiscRegFile::readReg(int miscReg) { switch (miscReg) { - case MISCREG_Y: - return y; - case MISCREG_CCR: - return ccr; +// case MISCREG_Y: +// return y; +// case MISCREG_CCR: +// return ccr; case MISCREG_ASI: return asi; case MISCREG_FPRS: @@ -155,16 +155,16 @@ MiscReg MiscRegFile::readReg(int miscReg) return pil; case MISCREG_CWP: return cwp; - case MISCREG_CANSAVE: - return cansave; - case MISCREG_CANRESTORE: - return canrestore; - case MISCREG_CLEANWIN: - return cleanwin; - case MISCREG_OTHERWIN: - return otherwin; - case MISCREG_WSTATE: - return wstate; +// case MISCREG_CANSAVE: +// return cansave; +// case MISCREG_CANRESTORE: +// return canrestore; +// case MISCREG_CLEANWIN: +// return cleanwin; +// case MISCREG_OTHERWIN: +// return otherwin; +// case MISCREG_WSTATE: +// return wstate; case MISCREG_GL: return gl; @@ -225,12 +225,12 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) void MiscRegFile::setReg(int miscReg, const MiscReg &val) { switch (miscReg) { - case MISCREG_Y: - y = val; - break; - case MISCREG_CCR: - ccr = val; - break; +// case MISCREG_Y: +// y = val; +// break; +// case MISCREG_CCR: +// ccr = val; +// break; case MISCREG_ASI: asi = val; break; @@ -291,21 +291,21 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val) case MISCREG_CWP: cwp = val; break; - case MISCREG_CANSAVE: - cansave = val; - break; - case MISCREG_CANRESTORE: - canrestore = val; - break; - case MISCREG_CLEANWIN: - cleanwin = val; - break; - case MISCREG_OTHERWIN: - otherwin = val; - break; - case MISCREG_WSTATE: - wstate = val; - break; +// case MISCREG_CANSAVE: +// cansave = val; +// break; +// case MISCREG_CANRESTORE: +// canrestore = val; +// break; +// case MISCREG_CLEANWIN: +// cleanwin = val; +// break; +// case MISCREG_OTHERWIN: +// otherwin = val; +// break; +// case MISCREG_WSTATE: +// wstate = val; +// break; case MISCREG_GL: gl = val; break; |