diff options
author | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-02 18:04:42 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-02 18:04:42 -0500 |
commit | 592f35ac0ff8d525fad2dc606b53b4cd8b84fd69 (patch) | |
tree | cdd2cf069de41c1f1fbf58a567dd5d855dce769c /src/arch/sparc/miscregfile.cc | |
parent | 5c7192daedcd33d9f7deb42406002adf4f2ffb68 (diff) | |
download | gem5-592f35ac0ff8d525fad2dc606b53b4cd8b84fd69.tar.xz |
fix mostly floating point related
src/arch/sparc/floatregfile.cc:
fix fp read/writing to registers... looking for suggestions on cleaner ways if anyone has them
src/arch/sparc/isa/decoder.isa:
fix some fp implementations
src/arch/sparc/isa/formats/basic.isa:
add new fp op class that 0 cexec in fsr and sets rounding mode for the up comming op
src/arch/sparc/isa/includes.isa:
include the appropriate header files for the rounding code
src/arch/sparc/miscregfile.cc:
print fsr out when it's read/written and the Sparc traceflgas in on
src/cpu/exetrace.cc:
fix printing of float registers
--HG--
extra : convert_revision : 49faab27f2e786a8455f9ca0f3f0132380c9d992
Diffstat (limited to 'src/arch/sparc/miscregfile.cc')
-rw-r--r-- | src/arch/sparc/miscregfile.cc | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index 0fe3e96b2..8b612e8b4 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -232,6 +232,7 @@ MiscReg MiscRegFile::readReg(int miscReg) /** Floating Point Status Register */ case MISCREG_FSR: + DPRINTF(Sparc, "FSR read as: %#x\n", fsr); return fsr; case MISCREG_MMU_P_CONTEXT: @@ -337,10 +338,6 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) case MISCREG_PCR: case MISCREG_PIC: panic("Performance Instrumentation not impl\n"); - /** Floating Point Status Register */ - case MISCREG_FSR: - warn("Reading FSR Floating Point not implemented\n"); - break; case MISCREG_SOFTINT_CLR: case MISCREG_SOFTINT_SET: panic("Can read from softint clr/set\n"); @@ -488,6 +485,7 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val) /** Floating Point Status Register */ case MISCREG_FSR: fsr = val; + DPRINTF(Sparc, "FSR written with: %#x\n", fsr); break; case MISCREG_MMU_P_CONTEXT: |