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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-16 12:34:10 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-16 12:34:10 -0500 |
| commit | cd5b33b9ff4016427fa93655f4bbd9030c4f5612 (patch) | |
| tree | b449360088378c982f59568c0a2da0c45cb08c59 /src/arch/sparc/miscregfile.cc | |
| parent | 079dd454175ab7fdb3cc429f3cf199bd243c3776 (diff) | |
| download | gem5-cd5b33b9ff4016427fa93655f4bbd9030c4f5612.tar.xz | |
Fixes for SPARC_FS
configs/common/FSConfig.py:
Make a SPARC system create an IO bus.
src/python/m5/objects/T1000.py:
Create a T1000 platform
src/arch/sparc/miscregfile.cc:
Initialize the strand status register to the value legion provides.
src/cpu/exetrace.cc:
Truncate an ExtMachInst to a MachInst before comparing with Legion.
--HG--
extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
Diffstat (limited to 'src/arch/sparc/miscregfile.cc')
| -rw-r--r-- | src/arch/sparc/miscregfile.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index d9d7f4411..8ca3d66f9 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -94,7 +94,8 @@ void MiscRegFile::reset() hintp = 0; htba = 0; hstick_cmpr = 0; - strandStatusReg = 0; + //This is set this way in Legion for some reason + strandStatusReg = 0x50000; fsr = 0; implicitInstAsi = ASI_PRIMARY; implicitDataAsi = ASI_PRIMARY; |