diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-05-31 20:45:04 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-05-31 20:45:04 +0000 |
| commit | c432588981c2903fda4b00bf03ada3c2c04063f7 (patch) | |
| tree | 6230df1fe2f4032ef76973f8debcccfed6830285 /src/arch/sparc/miscregfile.cc | |
| parent | 62fde97bb2e40002e59d0185db419f6f72643a6f (diff) | |
| parent | 6b6de8aaae86ea8b0f416a175c547fc67bea804a (diff) | |
| download | gem5-c432588981c2903fda4b00bf03ada3c2c04063f7.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
src/cpu/simple/base.cc:
Hand merge
--HG--
extra : convert_revision : a2902ef9d917d22ffb9c7dfa2fd444694a65240d
Diffstat (limited to 'src/arch/sparc/miscregfile.cc')
| -rw-r--r-- | src/arch/sparc/miscregfile.cc | 60 |
1 files changed, 36 insertions, 24 deletions
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index f511ef454..0300694cc 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -142,27 +142,38 @@ void MiscRegFile::clear() MiscReg MiscRegFile::readRegNoEffect(int miscReg) { - switch (miscReg) { - case MISCREG_TLB_DATA: - /* Package up all the data for the tlb: - * 6666555555555544444444443333333333222222222211111111110000000000 - * 3210987654321098765432109876543210987654321098765432109876543210 - * secContext | priContext | |tl|partid| |||||^hpriv - * ||||^red - * |||^priv - * ||^am - * |^lsuim - * ^lsudm - */ - return bits((uint64_t)hpstate,2,2) | - bits((uint64_t)hpstate,5,5) << 1 | - bits((uint64_t)pstate,3,2) << 2 | - bits((uint64_t)lsuCtrlReg,3,2) << 4 | - bits((uint64_t)partId,7,0) << 8 | - bits((uint64_t)tl,2,0) << 16 | - (uint64_t)priContext << 32 | - (uint64_t)secContext << 48; + // The three miscRegs are moved up from the switch statement + // due to more frequent calls. + + if (miscReg == MISCREG_GL) + return gl; + if (miscReg == MISCREG_CWP) + return cwp; + if (miscReg == MISCREG_TLB_DATA) { + /* Package up all the data for the tlb: + * 6666555555555544444444443333333333222222222211111111110000000000 + * 3210987654321098765432109876543210987654321098765432109876543210 + * secContext | priContext | |tl|partid| |||||^hpriv + * ||||^red + * |||^priv + * ||^am + * |^lsuim + * ^lsudm + */ + return bits((uint64_t)hpstate,2,2) | + bits((uint64_t)hpstate,5,5) << 1 | + bits((uint64_t)pstate,3,2) << 2 | + bits((uint64_t)lsuCtrlReg,3,2) << 4 | + bits((uint64_t)partId,7,0) << 8 | + bits((uint64_t)tl,2,0) << 16 | + (uint64_t)priContext << 32 | + (uint64_t)secContext << 48; + } + + switch (miscReg) { + //case MISCREG_TLB_DATA: + // [original contents see above] //case MISCREG_Y: // return y; //case MISCREG_CCR: @@ -207,8 +218,9 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg) return tl; case MISCREG_PIL: return pil; - case MISCREG_CWP: - return cwp; + //CWP, GL moved + //case MISCREG_CWP: + // return cwp; //case MISCREG_CANSAVE: // return cansave; //case MISCREG_CANRESTORE: @@ -219,8 +231,8 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg) // return otherwin; //case MISCREG_WSTATE: // return wstate; - case MISCREG_GL: - return gl; + //case MISCREG_GL: + // return gl; /** Hyper privileged registers */ case MISCREG_HPSTATE: |