diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-06 18:47:42 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-06 18:47:42 -0500 |
| commit | 8ffd12e807bd05a57bbe8857dbff0ecaf217fe64 (patch) | |
| tree | 6515ebc54b8b0647259f06ed0aa836d5424042c3 /src/arch/sparc/miscregfile.cc | |
| parent | 310d8f0992637d69e270cac727ba0ff968cdb6ea (diff) | |
| parent | c7a1fdacd6f378dcd1245aab289d497f801398f6 (diff) | |
| download | gem5-8ffd12e807bd05a57bbe8857dbff0ecaf217fe64.tar.xz | |
merge my index fix and lisa's fix
--HG--
extra : convert_revision : 5f2c7d46c96fa061bbfb66edf188d405ca600020
Diffstat (limited to 'src/arch/sparc/miscregfile.cc')
| -rw-r--r-- | src/arch/sparc/miscregfile.cc | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index 0fe3e96b2..8b612e8b4 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -232,6 +232,7 @@ MiscReg MiscRegFile::readReg(int miscReg) /** Floating Point Status Register */ case MISCREG_FSR: + DPRINTF(Sparc, "FSR read as: %#x\n", fsr); return fsr; case MISCREG_MMU_P_CONTEXT: @@ -337,10 +338,6 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) case MISCREG_PCR: case MISCREG_PIC: panic("Performance Instrumentation not impl\n"); - /** Floating Point Status Register */ - case MISCREG_FSR: - warn("Reading FSR Floating Point not implemented\n"); - break; case MISCREG_SOFTINT_CLR: case MISCREG_SOFTINT_SET: panic("Can read from softint clr/set\n"); @@ -488,6 +485,7 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val) /** Floating Point Status Register */ case MISCREG_FSR: fsr = val; + DPRINTF(Sparc, "FSR written with: %#x\n", fsr); break; case MISCREG_MMU_P_CONTEXT: |