Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts

getting touched.

configs/common/FSConfig.py:
    Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
    we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
    Fix AsiIsNucleus spelling with respect to header file
    Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
    Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
    switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
    Flesh out priviledgedString with hypervisor checks
    Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
    insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
    Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
    flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
    add an IPR traceflag
src/mem/request.hh:
    Fix a bad assert() in request

--HG--
extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28

1 files changed, 11 insertions, 2 deletions

diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index 67690bdb3..8f2bcf4ae 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -280,6 +280,7 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
     switch (miscReg) {
         // tick and stick are aliased to each other in niagra
       case MISCREG_TICK:
+      case MISCREG_STICK:
       case MISCREG_PRIVTICK:
         // I'm not sure why legion ignores the lowest two bits, but we'll go
         // with it
@@ -296,10 +297,10 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
         /** Floating Point Status Register */
       case MISCREG_FSR:
         panic("Floating Point not implemented\n");
-      case MISCREG_STICK:
-      case MISCREG_SOFTINT:
       case MISCREG_SOFTINT_CLR:
       case MISCREG_SOFTINT_SET:
+        panic("Can read from softint clr/set\n");
+      case MISCREG_SOFTINT:
       case MISCREG_TICK_CMPR:
       case MISCREG_STICK_CMPR:
       case MISCREG_HPSTATE:
@@ -499,20 +500,28 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
 
       case MISCREG_SCRATCHPAD_R0:
         scratchPad[0] = val;
+        break;
       case MISCREG_SCRATCHPAD_R1:
         scratchPad[1] = val;
+        break;
       case MISCREG_SCRATCHPAD_R2:
         scratchPad[2] = val;
+        break;
       case MISCREG_SCRATCHPAD_R3:
         scratchPad[3] = val;
+        break;
       case MISCREG_SCRATCHPAD_R4:
         scratchPad[4] = val;
+        break;
       case MISCREG_SCRATCHPAD_R5:
         scratchPad[5] = val;
+        break;
       case MISCREG_SCRATCHPAD_R6:
         scratchPad[6] = val;
+        break;
       case MISCREG_SCRATCHPAD_R7:
         scratchPad[7] = val;
+        break;
 
       default:
         panic("Miscellaneous register %d not implemented\n", miscReg);