Merge zizzer:/bk/sparcfs

into  zower.eecs.umich.edu:/eecshome/m5/newmemmid

src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.hh:
    hand merge

--HG--
extra : convert_revision : 34f50dc5e6e22096cb2c08b5888f2b0fcd418f3e

1 files changed, 64 insertions, 8 deletions

diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index 6bc04b583..90d7229e0 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -32,7 +32,6 @@
 #ifndef __ARCH_SPARC_MISCREGFILE_HH__
 #define __ARCH_SPARC_MISCREGFILE_HH__
 
-#include "arch/sparc/asi.hh"
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/isa_traits.hh"
 #include "arch/sparc/types.hh"
@@ -93,6 +92,40 @@ namespace SparcISA
         /** Floating Point Status Register */
         MISCREG_FSR,
 
+        /** MMU Internal Registers */
+        MISCREG_MMU_P_CONTEXT,
+        MISCREG_MMU_S_CONTEXT,
+        MISCREG_MMU_PART_ID,
+        MISCREG_MMU_LSU_CTRL,
+
+        MISCREG_MMU_ITLB_C0_TSB_PS0,
+        MISCREG_MMU_ITLB_C0_TSB_PS1,
+        MISCREG_MMU_ITLB_C0_CONFIG,
+        MISCREG_MMU_ITLB_CX_TSB_PS0,
+        MISCREG_MMU_ITLB_CX_TSB_PS1,
+        MISCREG_MMU_ITLB_CX_CONFIG,
+        MISCREG_MMU_ITLB_SFSR,
+        MISCREG_MMU_ITLB_TAG_ACCESS,
+
+        MISCREG_MMU_DTLB_C0_TSB_PS0,
+        MISCREG_MMU_DTLB_C0_TSB_PS1,
+        MISCREG_MMU_DTLB_C0_CONFIG,
+        MISCREG_MMU_DTLB_CX_TSB_PS0,
+        MISCREG_MMU_DTLB_CX_TSB_PS1,
+        MISCREG_MMU_DTLB_CX_CONFIG,
+        MISCREG_MMU_DTLB_SFSR,
+        MISCREG_MMU_DTLB_SFAR,
+        MISCREG_MMU_DTLB_TAG_ACCESS,
+
+        /** Scratchpad regiscers **/
+        MISCREG_SCRATCHPAD_R0,
+        MISCREG_SCRATCHPAD_R1,
+        MISCREG_SCRATCHPAD_R2,
+        MISCREG_SCRATCHPAD_R3,
+        MISCREG_SCRATCHPAD_R4,
+        MISCREG_SCRATCHPAD_R5,
+        MISCREG_SCRATCHPAD_R6,
+        MISCREG_SCRATCHPAD_R7
         MISCREG_NUMMISCREGS
     };
 
@@ -150,8 +183,32 @@ namespace SparcISA
         /** Floating point misc registers. */
         uint64_t fsr;		// Floating-Point State Register
 
-        ASI implicitInstAsi;
-        ASI implicitDataAsi;
+        /** MMU Internal Registers */
+        uint16_t priContext;
+        uint16_t secContext;
+        uint16_t partId;
+        uint64_t lsuCtrlReg;
+
+        uint64_t iTlbC0TsbPs0;
+        uint64_t iTlbC0TsbPs1;
+        uint64_t iTlbC0Config;
+        uint64_t iTlbCXTsbPs0;
+        uint64_t iTlbCXTsbPs1;
+        uint64_t iTlbCXConfig;
+        uint64_t iTlbSfsr;
+        uint64_t iTlbTagAccess;
+
+        uint64_t dTlbC0TsbPs0;
+        uint64_t dTlbC0TsbPs1;
+        uint64_t dTlbC0Config;
+        uint64_t dTlbCXTsbPs0;
+        uint64_t dTlbCXTsbPs1;
+        uint64_t dTlbCXConfig;
+        uint64_t dTlbSfsr;
+        uint64_t dTlbSfar;
+        uint64_t dTlbTagAccess;
+
+        uint64_t scratchPad[8];
 
         // These need to check the int_dis field and if 0 then
         // set appropriate bit in softint and checkinterrutps on the cpu
@@ -192,14 +249,14 @@ namespace SparcISA
         void setRegWithEffect(int miscReg,
                 const MiscReg &val, ThreadContext * tc);
 
-        ASI getInstAsid()
+        int getInstAsid()
         {
-            return implicitInstAsi;
+            return priContext | (uint32_t)partId << 13;
         }
 
-        ASI getDataAsid()
+        int getDataAsid()
         {
-            return implicitDataAsi;
+            return priContext | (uint32_t)partId << 13;
         }
 
         void serialize(std::ostream & os);
@@ -213,7 +270,6 @@ namespace SparcISA
         bool isHyperPriv() { return (hpstate & (1 << 2)); }
         bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
         bool isNonPriv() { return !isPriv(); }
-        inline void setImplicitAsis();
     };
 }