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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-03-05 11:00:44 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-03-05 11:00:44 +0000 |
| commit | 6a19b64de2044e5b166a9883be6531166cd69900 (patch) | |
| tree | e463581d5611ac0a2223a292cc4d1231f3de6b1f /src/arch/sparc/miscregfile.hh | |
| parent | 5498d5298577c07189ff3f7026eba5c1ee09cc1b (diff) | |
| parent | ba042842c61339e33c0b684f9854e8fe818160fe (diff) | |
| download | gem5-6a19b64de2044e5b166a9883be6531166cd69900.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
--HG--
extra : convert_revision : b585cea2221377eb2fceea8976c46a17c0034f51
Diffstat (limited to 'src/arch/sparc/miscregfile.hh')
| -rw-r--r-- | src/arch/sparc/miscregfile.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index 66c9f17df..4207de823 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -259,6 +259,9 @@ namespace SparcISA ThreadContext *tc); MiscReg readFSRegWithEffect(int miscReg, ThreadContext * tc); + // Update interrupt state on softint or pil change + void checkSoftInt(ThreadContext *tc); + /** Process a tick compare event and generate an interrupt on the cpu if * appropriate. */ void processTickCompare(ThreadContext *tc); |